HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 356

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.20.5.2
Table 114.
Figure 45.
Intel
Datasheet
356
S
Sr
S
®
11X0_XXX
11X0_XXX
11X0_XXX
5100 Memory Controller Hub Chipset
SMBUS write
SMBUS read
Configuration Register Read Protocol
Configuration reads are accomplished through an SMBus write(s) and later followed by
an SMBus read. The write sequence is used to initialize the Bus Number, Device,
Function, and Register Number for the configuration access. The writing of this
information can be accomplished through any combination of the supported SMBus
write commands (Block, Word or Byte). The Internal Command field for each write
should specify Read DWord.
After all the information is set up, the last write (End bit is set) initiates an internal
configuration read. If the data is not available before the slave interface acknowledges
this last write command (ACK), the slave will “clock stretch” until the data returns to
the SMBus interface unit. If an error occurs during the internal access, the last write
command will receive a NAK. A status field indicates abnormal termination and contains
status information such as target abort, master abort, and timeouts. The status field
encoding is defined in
Status Field Encoding for SMBus Reads
Examples of configuration reads are illustrated in
Read (Block Write/Block Read, PEC Enabled)”
Read (Write Bytes/Read Bytes, PEC Enabled).”
Code (PEC) enabled. If the master does not support PEC, then bit 4 of the command
would be cleared and there would not be a PEC phase. For the definition of the diagram
conventions below, refer to the System Management Bus (SMBus) Specification,
Version 2.0. For SMBus read transactions, the last byte of data (or the PEC byte if
enabled) is NAKed by the master to indicate the end of the transaction. For diagram
compactness, “Register Number” is also sometimes referred to as “Reg Number” or
“Register”.
SMBus Configuration Read (Block Write/Block Read, PEC Enabled)
Figure 46, “SMBus Configuration Read (Word Writes/Word Reads, PEC Enabled)”
example using word reads. The final data is a byte read.
7
6
5
4
3:1
0
W A
R A
Bit
W A
Internal Timeout. This bit is set if an SMBus request is not completed
Reserved
Internal Master Abort
Internal Target Abort
Reserved
Successful
Cmd = 11010010
Cmd = 11010010
Byte Count = 5
A
A
A
Table 114, “Status Field Encoding for SMBus Reads.”
Byte Count = 4
Data[15:8]
Status
A
A
A
Description
Data[31:24]
Bus Number
Data[7:0]
Reg Number [15:8]
Intel
through
All of these examples have Packet Error
®
Figure 45, “SMBus Configuration
5100 MCH Chipset—Functional Description
A
A
A
Figure 47, “SMBus Configuration
A
Device/Function
Data[23:16]
PEC
PEC
Order Number: 318378-005US
N P
A
A
CLOCK STRETCH
Reg Number[7:0]
July 2009
is an
A P
A