HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 233

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.20
July 2009
Order Number: 318378-005US
PEXDEVSTS - PCI Express* Device Status Register
Device:
Function:
Offset:
9
8
7:5
4
3
2
1
0
Device:
Function:
Offset:
15:6
Bit
Bit
RO
RO
RW
RO
RO
RW
RW
RW
RV
Attr
Attr
®
5100 MCH Chipset
8
0
74h
8
0
76h
0
0
000
0
0
0
0
0
0h
Default
Default
PFEN: Phantom Functions Enable
The DMA Engine device does not implement phantom functions so setting this bit
has no effect. Hardwired to 0h
ETFEN: Extended Tag Field Enable:
The DMA Engine device does not implement extended tags so setting this bit has no
effect.
MPS: Max_Payload_Size:
The DMA Engine device must not generate packets on any PCI Express* interface
which exceeds the length allowed with this field.
000: 128 bytes max payload size
001: 256 bytes max payload size
010: 512 bytes max payload size
011: 1024 bytes max payload size
100: 2048 bytes max payload size
101: 4096 bytes max payload size
Note:
ENRORD: Enable Relaxed Ordering
No relaxed ordering is supported by the Intel
URREN: Unsupported Request Reporting Enable
For an integrated DMA Engine device, this bit is irrelevant. Hardwired to 0h
FERE: Fatal Error Reporting Enable:
This bit controls the reporting of fatal errors internal to the DMA Engine device
0: Fatal error reporting is disabled
1: Fatal error reporting is enabled
NFERE: Non-Fatal Error Reporting Enable
This bit controls the reporting of non fatal errors internal to the DMA Engine device
in the PCI Express* port.
0: Non Fatal error reporting is disabled
1: Non Fatal error reporting is enabled
This has no effect on the Intel
not report any non-fatal errors.
CERE: Correctable Error Reporting Enable
This bit controls the reporting of correctable errors internal to the DMA Engine
device in the PCI Express* port.
0: Correctable error reporting is disabled
1: Correctable Fatal error reporting is enabled
This has no effect on the Intel
not report any correctable errors.
Reserved
This field has no impact internally to the Intel
maximum payload size of the TLPs that appear on the PCI Express* port is
governed by the PEXDEVCTRL.MPS for that port defined in
3.8.11.4, “PEXDEVCTRL[7:2,0] - PCI Express* Device Control Register.”
®
®
5100 MCH Chipset DMA Engine device as it does
5100 MCH Chipset DMA Engine device as it does
Description
Description
Intel
®
®
5100 MCH Chipset. Hardwired to 0h.
5100 Memory Controller Hub Chipset
®
5100 MCH Chipset and the
Section
Datasheet
233