HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 294

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.4.3
5.4.3.1
5.4.3.2
Intel
Datasheet
294
®
5100 Memory Controller Hub Chipset
Interrupt Redirection
The XAPIC architecture provides for lowest priority delivery through interrupt
redirection by the Intel
XAPIC message, the chipset may redirect the interrupt to another agent. Redirection of
interrupts can be applied to both I/O interrupts and IPIs.
XTPR Registers
To accomplish redirection, the Intel
Task Priority registers (XTPRs), one for each logical processor (a thread is considered a
logical processor). Each register contains the following fields:
The XTPR registers are modified by a front side bus XTPR_Update transaction. In
addition, the XTPR registers can be modified by software.
In addition, XTPR0 also contains a bit for Global Cluster Mode bit used in redirection of
logical destination mode messages. This bit indicates to the Intel
that destination field of the message is flat or cluster (note that the XAPIC message
indicates whether the destination mode is physical or logical). This bit is also updated
by an XTPR_Update transaction (FSBxAa[3]#) and is also programmable through
configuration space. The default logical mode at reset is flat.
More details on the Intel
register definition in
The XTPR special cycle must guarantee that the XTPR register is updated for interrupt
redirection in a consistent manner. For reproducibility, there needs to be an internal
serialization point after which subsequent interrupts will be redirected based on the
updated XTPR value.
Redirection Algorithm
Redirection is performed if an interrupt redirection hint bit (A[3]) is set. See
and
which processor the interrupt will be redirected.
1. Agent priority (Task Priority)
2. APIC enable bit (TPR Enable)
3. Logical APIC ID (LOGID)
4. Processor physical APIC ID (PHYSID)
1. If A[3] = 1, then this is a redirection (also known as “lowest priority”) interrupt
2. FLAT: If Destination Mode = 1 (A[2] for I/O, FSBxAb[5]# for IPIs) and
3. CLUSTER: If Destination Mode = 1 (A[2] for I/O, FSBxAb[5]# for IPI’s) and
request. Proceed to the next step.
XTPR[0].CLUSTER is disabled (0) in the XTPR, then this is Flat-Logical Destination
Mode. (Otherwise, proceed to the next step). To select the arbitration pool, for each
XTPR register: Note that Cluster Mode is not supported and should always be
disabled.
If (A[19:12] (DID) AND XTPR[n].LOGID[7:0]) > 0h
AND XTPR[n].TPREN =1
then XTPR[n] is included in the arbitration pool.
SC.XTPR[0].CLUSTER is enabled (1) in the XTPR, then this is Clustered-Logical
Destination Mode. (Otherwise, proceed to the next step).
To select the arbitration pool:
If (A[19:16] (DID[7:4]) == XTPR[n].LOGID[7:4])
AND ((A[15:12] (DID[3:0]) AND XTPR[n].LOGID[3:0]) >0h)
Section 5.4
for naming conventions. Below is the algorithm used in determining to
Section 3.8.4, “Interrupt Redirection Registers”
®
®
5100 MCH Chipset. If the redirectable “hint bit” is set in the
5100 MCH Chipset XTPR registers are described in the XTPR
®
5100 MCH Chipset implements a set of External
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
®
5100 MCH Chipset
Figure 20
July 2009