HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 98

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.3.1
3.8.3.2
Intel
Datasheet
98
®
5100 Memory Controller Hub Chipset
The MCH allows programmable memory attributes on 13 Legacy memory segments of
various sizes in the 640 kB to 1 MB address range. Seven Programmable Attribute Map
(PAM) Registers are used to support these features.
Each PAM Register controls one or two regions, typically 16 kB in size
PAM0 - Programmable Attribute Map Register 0
This register controls the read, write, and shadowing attributes of the BIOS area which
extends from 0F 0000h - 0F FFFFh.
Two bits are used to specify memory attributes for each memory segment. These bits
apply to both host accesses and PCI initiator accesses to the PAM areas. These
attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory
segment are claimed by the MCH and directed to main memory. Conversely, when RE =
0, the host read accesses are directed to ESI (ICH9R) to be directed to the PCI bus.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding
memory segment are claimed by the MCH and directed to main memory. Conversely,
when WE = 0, the host write accesses are directed to ESI (ICH9R) to be directed to the
PCI bus.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0,
the segment is Read Only.
PAM1 - Programmable Attribute Map Register 1
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0C 0000h-0C 7FFFh.
Device:
Function:
Offset:
Device:
Function:
Offset:
7:6
5:4
3:0
7:6
Bit
Bit
Attr
Attr
RW
RV
RV
RV
16
0
59h
16
0
5Ah
Default
Default
00
00
0h
00
Reserved
ESIENABLE0: 0F0000-0FFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0F0000 to 0FFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding: Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
Reserved
Reserved
Intel
®
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009