HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 320

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.13.7.1
5.13.8
Figure 32.
5.13.9
5.13.10
Intel
Datasheet
320
®
5100 Memory Controller Hub Chipset
Credit Update Mechanism, Flow Control Protocol (FCP)
After reset, credit information is initialized with the values indicated in
Express* Credit Mapping for Inbound Transactions”
initialization protocol defined in the PCI Express* Base Specification, Rev. 1.0a. Since
the MCH supports only VC0, only this channel is initialized.
Transaction Layer
The PCI Express* Transaction Layer is responsible for sending read and write
operations between components. This is the PCI Express* layer which actually moves
software visible data between components. The transaction layer provides the
mechanisms for:
Figure 32, “PCI Express* Packet Visibility By Transaction Layer”
the transaction layer on a PCI Express* packet. Some transaction layer packets have
only a header (e.g., read request). Some transaction layer packets have a header
followed by data (e.g., write requests and read completions).
PCI Express* Packet Visibility By Transaction Layer
DMA Engine Implementation
The MCH will support the DMA Engine technology on all PCI Express* Ports for I/O
performance acceleration, cost optimization, and reduced CPU utilization.
DMA Engine Usage Model
DMA Engine architecture originally supported two fundamental programming models.
• Software configuration of components
• Communication between the processor bus and different I/O technologies
• Communication between the memory and different I/O technologies
• Four Channel DMA Engine for performing basic operations such as memory-to-
• DMA Engine related configuration registers
• A Hardware Model where this is no assistance from operating system level software
• A Software Model where there is a DMA Engine driver that enables access to DMA
memory, and memory-to-MMIO transfer with a byte aligned granularity.
and thus an I/O device driver cannot directly access DMA Engine MMIO registers
(only the I/O device can access them).
Engine resources by I/O device drivers. Thus, the I/O device driver can access DMA
Engine MMIO registers.
Hdr
Hdr
Intel
Payload
®
5100 MCH Chipset—Functional Description
by following the flow control
Order Number: 318378-005US
illustrates the scope of
Table 98, “PCI
July 2009