HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 286

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 90.
5.2.6
5.2.6.1
Intel
Datasheet
286
®
5100 Memory Controller Hub Chipset
SPD Addressing
DRAM ECC Code
The Intel
aka SECC). As applied by the Intel
properties:
See also
The rank address is also encoded into the ECC algorithm. This allows a degree of
protection against address line glitches, but not consistent stuck-at type address line
faults.
Inbound ECC Code Layout for Memory Interface
When the Intel
an ECC encoding scheme is used to minimize data corruption. The ECC coding scheme
uses code words based upon the unit of access, a cache line. Each 64-byte cache line
plus eight bytes of parity form two ECC code words. A cache line on the Intel
MCH Chipset requires a burst of eight DDR2 data bus transfers (BL=8). Each half burst
or 4x nine bytes comprises a code word. Each code word can then be considered a half
cache line. In a burst of eight, the first four encoded values (72 bits each) form the first
code word, and the second four encoded values form the second code word.
The ECC code layout is systematic, in other words, the data is separated from the
check-bits rather than all being encoded together. It consists of 32 8-bit data symbols
and four 8-bit check-bit symbols (72 nibbles, 288 bits). The symbols are further broken
down into nibbles.
The ECC code corrects any two adjacent 8-bit symbols in error. The code layout ensures
that the four consecutive nibbles transferred, during a burst of four DDR2 data bus
transfers, form 16 contiguous bits or two adjacent symbols in a single code word. The
symbols are arranged so that the data from every x4 DRAM is mapped to two adjacent
symbols of a single code word, so the failure of any single x4 DRAM device can be
corrected. If the device corresponding to nibble 0 fails, nibbles 0–3 (16 bits, two
symbols) in the first code word, and nibbles 72–75 in the second code word, will be
affected and are correctable by the code.
The ECC code is transferred across the DDR2 channel, or equivalently, the DDR2 data
bus in symbols. The symbols are mapped to DRAM bits in the DIMM for cache line
transfers. The Check Bytes signals as defined by the Intel
limited to ECC data bytes in this implementation; all of the Check Byte signals and Data
• Correction of any x4 device failure (e.g. stuck at 0)
• 100% detection of x4 single device failure in addition to single bit soft error in
• Detection of all two wire faults on the DIMMs. This includes any pair of single bit
Channel
another device.
errors.
0
®
Section 5.2.4.7, “Single Device Data Correction (SDDC)
5100 MCH Chipset supports the DRAM device failure correction code (SDDC
®
SLOT
5100 MCH Chipset transfers data to and from the MCH DDR2 memory,
0
1
2
3
Slave Address
SA[2:0]
0
1
2
3
®
5100 MCH Chipset, this code has the following
Channel
1
Intel
®
5100 MCH Chipset—Functional Description
SLOT
0
1
2
3
®
Slave Address
5100 MCH Chipset are not
SA[2:0]
Order Number: 318378-005US
4
5
6
7
Support”.
®
5100
July 2009