HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 263

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
Table 78.
4.2.4
4.2.5
July 2009
Order Number: 318378-005US
Read and write transactions may be directed to different destinations with in the range
C 0000h to D FFFFh. Historically, these blocks were used to shadow ISA device BIOS
code. For the Intel
space to PCI devices requiring memory space below 1 MB. The range is divided into
eight sub-ranges. These ranges are defined by SC.PAM registers. There is a PAM
register for each sub-range that defines the routing of reads and writes.
PAM Settings
The power-on default for these segments is mapped read/write to the ESI port
(ICH9R). Software should not set cacheable memory attributes for any of these ranges,
unless both reads and writes are mapped to main memory. Chipset functionality is not
guaranteed if this region is cached in any mode other than both reads and writes being
mapped to main memory.
For locks to this region, the Intel
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound accesses are expected, the C and D
segments MUST be programmed to send accesses to DRAM.
Lower System BIOS Area (E 0000h–E FFFFh)
This 64-kB area, from E 0000h to E FFFFh, is divided into four, 16-kB segments. Each
segment can be assigned independent read and write attributes through the SC.PAM
registers. This area can be mapped either the ESI port (ICH9R) or to main memory.
Historically this area was used for BIOS ROM. Memory segments that are disabled are
not remapped elsewhere.
The power-on default for these segments is to map them to the ESI port (ICH9R).
Software should not set cacheable memory attributes for any of these ranges unless
both read and write transactions are mapped to main memory. Chipset functionality is
not guaranteed if this region is cached.
For locks to this region, the Intel
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound transactions are expected, the E segment
MUST be programmed to send these transactions to DRAM.
Upper System BIOS Area (F 0000h–F FFFFh)
This area is a single, 64-kB segment, from E 0000h - F FFFFh. This segment can be
assigned read and write attributes through the SC.PAM registers. The power-on default
is set to read/write disabled with transactions forwarded to the ESI port (ICH9R). By
manipulating the read/write attributes, the MCH can “shadow” BIOS into the main
system memory. When disabled, this segment is not remapped.
For locks to this region, the Intel
guarantee the atomicity of locked access to this range when writes and reads are
mapped to separate destinations. If inbound transactions are expected, the F segment
MUST be programmed to send these transactions to DRAM.
00
01
10
11
PAM [5:4]/
[1:0]
®
5100 MCH Chipset
ESI
ESI
Main Memory
Main Memory
Write Destination
®
5100 MCH Chipset, these regions are used to provide address
®
®
®
ESI
Main Memory
ESI
Main Memory
Read Destination
5100 MCH Chipset will complete them, but does not
5100 MCH Chipset will complete them, but does not
5100 MCH Chipset will complete, but does not
Mapped to ESI Port
Memory Write Protect
In-Line Shadowed
Mapped to main memory
Intel
®
5100 Memory Controller Hub Chipset
Result
Datasheet
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