HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 109

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.6.2
3.8.6.3
3.8.6.4
July 2009
Order Number: 318378-005US
FSBC1: Processor Bus Controller
This register allows control of the FSB1 Processor Bus.
FSBS[1:0] - Processor Bus Status Register
This register holds status from the Processor Busses.
XTPR[15:0] - External Task Priority Register
These registers control redirectable interrupt priority for xAPIC agents connected to the
MCH. Up to eight agents on each bus are supported. These agents may be two dual
core processor sockets each with four threads (two threads per core). The contents of
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:5
29:0
31:2
4:3
2:0
Bit
Bit
Bit
31
30
1
0
®
Attr
Attr
RW
RO
RO
RV
RV
RV
RWST
5100 MCH Chipset
Attr
16
0
F0h
RV
RV
16
0
78h
16
0
7Ch, 74h
0FFA800Fh
Default
Default
0h
0
0
0
0
Default
3FAh
11
0
Reserved
DisFSB1: Disable FSB1
0: Do not disable the FSB1 (default)
1: Disables the FSB1.
Disables all logic and Vterm circuits associated with FSB1 and must be used in
conjunction with PROCENABLE.FSBEN.
Reserved
Reserved
2SOCKET: 2 Sockets present on this FSB
Set when the Intel
there are more than 1 processors present on this FSB.
2CORE: 2 Cores present
Set when the Intel
there is more than 1 core in a processor.
Reserved
FSBEN: FSB1 and FSB0 Enable
The field is defined as the following:
00: reserved
01: FSB1 is disabled. FSB0 is enabled.
10: FSB1 is enabled. FSB0 is disabled.
11: FSB1 is enabled. FSB0 is enabled. (default)
Hard reset is needed after changing value in this register.
Reserved
®
®
5100 MCH Chipset has seen Ab[22] asserted, indicating
5100 MCH Chipset has seen Ab[30] asserted, indicating
Description
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
109