HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 118

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.12
3.8.8.13
3.8.8.14
Intel
Datasheet
118
®
5100 Memory Controller Hub Chipset
SEC_LT[7:2] - Secondary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the secondary interface. It does not affect/influence PCI Express* functionality.
IOBASE[7:2] - I/O Base Register
The I/O Base and I/O Limit registers (see
Register”) define an address range that is used by the PCI Express* port to determine
when to forward I/O transactions from one interface to the other using the following
formula:
Only the upper 4 bits are programmable. For the purpose of address decode, address
bits A[11:0] are treated as 0. The bottom of the defined I/O address range will be
aligned to a 4 kB boundary while the top of the region specified by IO_LIMIT will be one
less than a 4 kB multiple. Refer to
4.5.2, “Outbound I/O Access.”
IOLIM[7:2] - I/O Limit Register
The I/O Base and I/O Limit registers define an address range that is used by the PCI
Express* bridge to determine when to forward I/O transactions from one interface to
the other using the following formula:
Only the upper 4 bits of this register are programmable. For the purpose of address
decode, address bits A[11:0] of the I/O limit register is treated as FFFh.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
7:0
7:4
3:0
7:4
Bit
Bit
Bit
IO_BASE <= A[15:12] <= IO_LIMIT
IO_BASE <= A[15:12] <= IO_LIMIT
Attr
Attr
Attr
RW
RW
RO
RO
2-3, 4-7
0
1Bh
2-3, 4-7
0
1Ch
2-3, 4-7
0
1Dh
Default
Default
Default
00h
0h
0h
0h
Slat_tmr: Secondary Latency Timer
Not applicable to PCI Express*. Hardwired to 00h.
IOBASE: I/O Base Address
Corresponds to A[15:12] of the I/O addresses at the PCI Express* port.
IOCAP: I/O Address capability
0h – 16 bit I/O addressing, (supported)
1h – 32 bit I/O addressing,
others - Reserved.
The MCH does not support 32 bit addressing, so these bits are hardwired to 0.
IOLIMIT: I/O Address Limit
Corresponds to A[15:12] of the I/O addresses at the PCI Express* port.
Section 4.5.1, “Special I/O Addresses”
Section 3.8.8.14, “IOLIM[7:2] - I/O Limit
Intel
®
Description
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
and
Section
July 2009