HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 360

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.20.6.3
Figure 52.
5.20.6.4
Table 115.
5.20.6.5
5.20.7
Intel
Datasheet
360
®
5100 Memory Controller Hub Chipset
Request Packet for SPD Byte Write
Upon receiving the SPDW command, the MCH generates the Byte Write Register
command sequence as shown in
indicates that the SIO command has completed by setting the WOD bit of the SPD
configuration register to 1.
Byte Write Register Timing
SPD Protocols
The Intel
5100 Memory Controller Hub Chipset Supported SPD Protocols.”
Intel
SPD Bus Timeout
If there is an error in the transaction, such that the SPD EEPROM does not signal an
acknowledge, the transaction will time out. The MCH will discard the cycle and set the
SBE bit of the SPD configuration register to 1 to indicate this error. The timeout
counter within the MCH begins counting after the last bit of data is transferred to the
DIMM, while the MCH waits for a response.
PCI Hot Plug* Support, GPIOSMBus
GPIOSMBus is the PCI Hot Plug* port. GPIOSMBus is a PCI Hot Plug* Virtual Pin Port
(VPP) that operates using the SM Bus Masters protocol as defined in System
Management Bus (SMBus) Specification, Version 2.0.
GPIOSMBus supplies support for PCI Hot Plug* devices. Support for PCI Express* is an
option described in PCI Express* Base Specification, Rev. 1.0a. The PCI Hot Plug*
model implies a PCI Hot Plug* controller per port which is identified to software as a
capability of the PCI-to-PCI Bridge configuration space.
PCI Hot Plug* support requires that the Intel
Hot Plug* messages to manage the states between the PCI Hot Plug* controller and the
device.
The PCI Express* form factor has an impact to the level of support required of the
MCH. For example, some of the PCI Hot Plug* messages are required only if the LED
indicators reside on the actual card and are accessed through the endpoint device. The
Intel
platform is not constrained to any particular form factor.
Intel
S
T
A
R
T
®
D
T
3
®
I
®
5100 MCH Chipset Supported SPD Protocols
5100 MCH Chipset supports all of the PCI Hot Plug* messages so that the
D
5100 Memory Controller Hub Chipset Supported SPD Protocols
T
2
I
Slave Address
®
D
T
1
I
5100 MCH Chipset supports the SPD protocols shown in
D
T
0
I
Random Byte Read
A
2
S
Byte Write
A
1
S
A
0
S
W
R
/
A
K
C
0
B
A
7
Figure 52, “Byte Write Register Timing.”
B
A
6
Byte Address
B
A
5
A
B
4
B
A
3
Intel
®
A
B
2
5100 MCH Chipset supports a set of PCI
®
A
B
1
5100 MCH Chipset—Functional Description
B
A
0
A
K
C
Order Number: 318378-005US
DATA
Table 115, “Intel®
The MCH
July 2009
A
C
K
O
S
T
P