HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 213

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.9.9.3
3.9.9.4
3.9.10
3.9.10.1
July 2009
Order Number: 318378-005US
MEMEINJADDRMAT: Error Injection Address Match Register
Contains the address match for error injection. The address mask register determines
which of the lower bits [11:6] are ignored for determining a match. Enabled on channel
basis by bit 31 of MEM[1:0]EINJMSK0
MEMEINJADDRMSK: Error Injection Address Mask Register
Contains the address match for error injection. The address mask register determines
which of the lower bits [11:6] are ignored for determining a match. Enabled on channel
basis by bit 31 of MEM[1:0]EINJMSK0
Memory Interface Control
DSRETC[1:0]: DRAM Self-Refresh Extended Timing and Control
This register sets the timing of operations to different ranks while the auto-refresh FSM
controls the DRAM command bus. This allows power intensive commands to be
staggered. Both fields should be set so as not to violate T
modes, the min value allowed for DRARTIM is T
refreshes can start on any rank and have to be spaced from the last autorefresh) while
the min value allowed for DSRENT is 2xT
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:0
Bit
31:0
15:6
15:8
5:0
Bit
Bit
Bit
RWST
Attr
RWST
®
Attr
RWST
RWST
Attr
Attr
5100 MCH Chipset
RV
16
1
206h, 204h
16
1
20Ch
16
1
210h
22, 21
0
144h
Default
0h
Default
Default
Default
14h
0000h
000h
00h
XORMSK: XOR mask bit for second device location
[15:8]: XOR mask for transfer 1 (lower half cache line) or 3 (upper half cache line).
[7:0]: XOR mask for transfer 0 (lower half cache line) or 2 (upper half cache line).
DRARTIM: auto-refresh timing- stagger of commands between ranks
SYSADDRMAT: System Address[35:6] match
Reserved
SYSADDRMSK: System Address[11:6] Mask
Address lines are ignored for match if the corresponding mask bit is set. By
default, no masking, an exact match is required.
RFC
/ N, because of CKE sharing.
RFC
Description
(because of CKE sharing, self-
Description
Description
Description
Intel
®
RFC
5100 Memory Controller Hub Chipset
. In both 4 rank and 6 rank
Datasheet
213