HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 299

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.7
July 2009
Order Number: 318378-005US
Chipset Generated Interrupts
The Intel
Express*. For these events, the chipset can be programmed to assert pins that the
system can route to an APIC controller. The following is a list of interrupts that can be
generated.
1. Chipset error - The Intel
2. PCI Express* error - The Intel
3. PCI Hot Plug* - The Intel
depending on severity. This can be routed by the system to generate an interrupt
at an interrupt controller (the Intel
The ERR[0] pin denotes a correctable and recoverable error. The ERR[1] pin
denotes an uncorrectable error from the Intel
denotes a fatal error output from the Intel
depending on severity. This can be routed by the system to generate an interrupt.
a.
(Deassert_HPGPE) or generates an MSI or a legacy interrupt on behalf of a PCI Hot
Plug* event.
a.
b. PCI Hot Plug* event from downstream. This could be either an MSI or a GPE
— MSI: Handled like a normal MSI interrupt (see
— GPE message: Upon receipt of a Assert_GPE message from PCI Express*, the
— Sideband signals: Some systems may choose to connect the interrupt via
Express* ports. These are in the form of inbound ERR_COR/UNC/FATAL
messages. The Intel
just like any internal Intel
change, Attn button, MRL sensor changed, power fault, etc. Each of these events
have a corresponding bit in the PCI Hot Plug* registers (Attention Button, Power
Indicator, Power Controller, Presence Detect, MRL Sensor, Port Capabilities/Slot
registers). This will generate an interrupt via the Assert_HPGPE, INTx, or an
MSI. Refer to
message.
Intel
generate an SCI (ACPI), this signal will be routed to the ICH9R appropriate
GPIO pin to match the GPE0_EN register settings. When the PCI Hot Plug*
event has been serviced, the Intel
Deassert_GPE message. At this point the Intel
Deassert_GPE message to ESI. There needs to be a tracking bit per PCI
Express* port to keep track of Assert/Deassert_GPE pairs. These tracking bits
should be OR’d together to determine whether to send the Assert_GPE/
Deassert_GPE message. When the Intel
matching Deassert_GPE message for that port, it will clear the corresponding
tracking bit. When all the tracking bits are cleared, the Intel
Chipset will send a Deassert_GPE message to the ESI port.
sideband signals directly to the ICH9R. No action is required from the Intel
5100 MCH Chipset.
The Intel
The Intel
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5100 MCH Chipset can trigger interrupts for chipset errors and for PCI
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5100 MCH Chipset
5100 MCH Chipset will send Assert_GPE signal to the ESI port. To
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5100 MCH Chipset can receive error indications from the PCI
5100 MCH Chipset generated PCI Hot Plug* event such as PresDet
Figure 21
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5100 MCH Chipset will assert the appropriate ERR signal
5100 MCH Chipset asserts appropriate ERR pin,
5100 MCH Chipset sends Assert_HPGPE
for the PCI Hot Plug* interrupt flow priority.
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5100 MCH Chipset error.
5100 MCH Chipset asserts appropriate ERR pin,
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5100 MCH Chipset pins ERR[2:0], MCERR).
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5100 MCH Chipset will receive a
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5100 MCH Chipset.
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5100 MCH Chipset receives a
5100 MCH Chipset. The ERR[2] pin
Intel
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Section
5100 MCH Chipset can send
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5100 Memory Controller Hub Chipset
5.5.3)
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5100 MCH
Datasheet
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