HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 319

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 98.
Table 99.
July 2009
Order Number: 318378-005US
PCI Express* Credit Mapping for Inbound Transactions
1. Root complexes and end points are permitted to advertise an infinite number of credits for completions.
PCI Express* Credit Mapping for Outbound Transactions
The credit advertisements for the MCH are shown in
Mapping for Inbound Transactions”
Outbound Transactions.”
(inbound) for both itself and the interfacing device. The rules governing flow control are
described in the PCI Express* Base Specification, Rev. 1.0a.
Inbound Posted Request
Header Credits (IPRH)
Inbound Posted Request
Data Credits (IPRD)
Inbound Non-Posted
Request Header Credits
(INPRH)
Inbound Non-Posted
Request Data Credits
(INPRD)
Completion Header
Credits (CPH) (outbound
request completions
received at the MCH)
Completion Data Credits
(CPD) (outbound request
completions (data)
received at the MCH)
Outbound Posted
Request Header Credits
(OPRH)
Outbound Posted
Request Data Credits
(OPRD)
Outbound Non-Posted
Request Header Credits
(ONPRH)
Outbound Non-Posted
Request Data Credits
(ONPRD)
Completion Header
Credits (CPLH) (inbound
request completions
from MCH)
Completion Data Credits
(CPLD) (inbound request
completions (data) from
the MCH)
Though the MCH implements finite queue structures as indicated in bracket for the completions on the inbound
side, by construction, it will never overflow since for each outbound request, the MCH allocates sufficient space
on the inbound side. In other words, guarantee by construction
Flow Control Type
Flow Control Type
®
5100 MCH Chipset
Tracks the number of inbound posted requests the agent is
capable of supporting. Each credit accounts for one posted
request.
Tracks the number of inbound posted data the agent is capable
of supporting. Each credit accounts for up to 16 bytes of data.
Tracks the number of non-posted requests the agent is capable
of supporting. Each credit accounts for one non-posted request.
Tracks the number of non-posted data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
Tracks the number of completion headers the agent is capable
of supporting.
Tracks the number of completion data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
Tracks the number of outbound posted requests the agent is
capable of supporting. Each credit accounts for one posted
request.
Tracks the number of outbound posted data the agent is
capable of supporting. Each credit accounts for up to 16 bytes
of data.
Tracks the number of non-posted requests the agent is capable
of supporting. Each credit accounts for one non-posted request.
Tracks the number of non-posted data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
Tracks the number of completion headers the agent is capable
of supporting.
Tracks the number of completion data the agent is capable of
supporting. Each credit accounts for up to 16 bytes of data.
Every PCI Express* device tracks the above six credit types
1
and
Table 99, “PCI Express* Credit Mapping for
Definition
Definition
Table 98, “PCI Express* Credit
Intel
®
5100 Memory Controller Hub Chipset
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Initial MCH
Initial MCH
0 (Infinite)
0 (Infinite)
(16) (x16)
(32) [x16]
216 (16x)
(16) [x8]
56 (x16)
108 (8x)
56 (16x)
32 (16x)
64 (16x)
64 (16x)
32 (x16)
(4) [x4]
(8) [x8]
(8) [x4]
14 (4x)
28 (8x)
54 (4x)
14 (4x)
28 (8x)
8 (16x)
16 (16)
16 (8x)
16 (4x)
32 (8x)
16 (4x)
32 (8x)
8 (x16)
16 (x8)
2 (4x)
4 (8x)
4 (4x)
8 (8x)
8 (4x)
2 (x4)
4 (x8)
8 (x4)
Datasheet
319