HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 57

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Figure 2.
July 2009
Order Number: 318378-005US
Intel
®
®
x16
5100 Memory Controller Hub Chipset Signal Diagram 32 GB Mode
5100 MCH Chipset
x8
x8
x8
x4
PEICOMPI, PERCOMPO
x4
x4
x4
x4
x4
x4
(ESI) PE0R{P/N}[3:0]
(ESI) PE0T{P/N}[3:0]
SPD0SMBDATA
PE2R{P/N}[3:0]
PE2T{P/N}[3:0]
PE3R{P/N}[3:0]
PE3T{P/N}[3:0]
PE4R{P/N}[3:0]
PE4T{P/N}[3:0]
PE5R{P/N}[3:0]
PE5T{P/N}[3:0]
PE6R{P/N}[3:0]
PE6T{P/N}[3:0]
PE7R{P/N}[3:0]
PE7T{P/N}[3:0]
GPIOSMBDATA
XDPSTB{P/N}#
TDIOCATHODE
CORECLK{P/N}
PEWIDTH[3:0]
CFGSMBDATA
XDPCOMCRES
XDPODTCRES
XDPSLWCRES
SPD0SMBCLK
FSBSLWCTRL
FSBODTCRES
FSBSLWCRES
XDPD[15:0]#
GPIOSMBCLK
ASYNCRFSH
CFGSMBCLK
TDIOANODE
PECLK{P/N}
COREVCCA
COREVSSA
FSB0VREF
FSB1VREF
PWRGOOD
ERR[2:0]#
XDPRDY#
PSEL[2:0]
PEVCCBG
PEVSSBG
FSBCRES
FSBVCCA
RESETI#
VCCDDR
PEVCCA
PEVSSA
TRST#
V3REF
VCCPE
RSVD
TDO
TMS
VTT
TCK
VCC
VSS
TDI
Express*
Interfaces
XD Port
Ground
Intel® 5100 MCH Chipset
SMBus
Power
Reset
Clock
JTAG
Misc
Bus
PCI
Channel 0
Channel 1
Bus 0
Bus 1
DDR2
DDR2
Front
Front
Side
Side
FSB0A[35:3]
FSB0ADSTB[1:0]#, FSB0ADS#
FSB0AP[1:0]#
FSB0BINIT#, FSB0BNR#
FSB0BPM[5:4]#
FSB0BPRI#
FSB0BREQ[1:0]#
FSB0D[63:0]#
FSB0DBI[3:0]#
FSB0DBSY#, FSB0DRDY#
FSB0DEFER#
FSB0DP[3:0]#
FSB0DSTB{P/N}[3:0]#
FSB0HIT#, FSB0HITM#
FSB0LOCK#
FSB0MCERR#
FSB0REQ[4:0]#
FSB0RESET#
FSB0RS[2:0]#
FSB0RSP#, FSB0TRDY#
FSB1A[35:3]
FSB1ADSTB[1:0]#, FSB1ADS#
FSB1AP[1:0]#
FSB1BINIT#, FSB1BNR#
FSB1BPM[5:4]#
FSB1BPRI#
FSB1BREQ[1:0]#
FSB1D[63:0]#
FSB1DBI[3:0]#
FSB1DBSY#, FSB1DRDY#
FSB1DEFER#
FSB1DP[3:0]#
FSB1DSTB{P/N}[3:0]#
FSB1HIT#, FSB1HITM#
FSB1LOCK#
FSB1MCERR#
FSB1REQ[4:0]#
FSB1RESET#
FSB1RS[2:0]#
FSB1RSP#, FSB1TRDY#
CH0_DQ[63:0]
CH0_DQS{P/N}[17:0]
CH0_CB[7:0]
CH0_A[15:0]
CH0_BA[2:0]
CH0_CAS#
CH0_RAS#
CH0_WE#
CH0_CS[3:0]#
CH0_CKE[3:0]
CH0_ODT[3:0]
CH0_DCLK{P/N}[3:0]
CH0_CRES{1/2}, CH0_CRESRET
CH0_DRVCRES, CH0_SLEWCRES
48GB_Mode
CH1_DQ[63:0]
CH1_DQS{P/N}[17:0]
CH1_CB[7:0]
CH1_A[15:0]
CH1_BA[2:0]
CH1_CAS#
CH1_RAS#
CH1_WE#
CH1_CS[3:0]#
CH1_CKE[3:0]
CH1_ODT[3:0]
CH1_DCLK{P/N}[3:0]
CH1_CRES{1/2}, CH1_CRESRET
CH1_DRVCRES, CH1_SLEWCRES
Intel
®
5100 Memory Controller Hub Chipset
Data
Com mand/
Address
Control
Clock
Data
Comm and/
Address
Control
Clock
Datasheet
57