HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 186

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.1.4
3.9.1.5
Table 58.
Intel
Datasheet
186
®
5100 Memory Controller Hub Chipset
MCDEF3: MCDEF Register 3
ERRPER: Error Period Prescaler
ERRPER is part of the RAS system for initiating sparing operations. Sparing will be
kicked off when a rank is assumed to be bad (“failed”) because a preprogrammed
number of correctable errors have been detected on that rank.
SER analysis determines a known expected correctable error rate and this is used to
“leak” expected errors from the count of actual correctable errors that have been
detected. This prevents a rank from being declared bad because of the natural
expected SER rate. The ERRPER register is a prescaler for the SER rate counters.
The Error Period counter increments the rank counters (one such counter per rank)
when it reaches the ERRPER value. The error period counter increments every 16
cycles. It is cleared on reset and wraps when it reaches this value.
timing characteristics of this register.
Non-zero CERRCNT (detected correctable errors) counts are decremented when rank
counters reach the programmed RANKTHRESHOLD values which should match the
expected SER rate. for the rank size
Timing Characteristics of ERRPER
Device:
Function:
Offset:
Device:
Function:
Offset:
Core Frequency
31:0
7:0
Bit
Bit
8
333 MHz
266 MHz
Attr
Attr
RO
RV
RV
16
1
44h
16
1
FCh
Default
Default
00h
0h
Per Increment
0
48 ns
60 ns
48GB_Mode: 48 GB mode operation status
0: 32 GB Mode is enabled utilizing up to four ranks/channel
1: 48 GB Mode is enabled utilizing up to six ranks/channel
B0: The value of the bit provides the strapped state of the 48GB_Mode input. The
48GB_Mode input is strapped High for 48 GB support over six ranks/channel. The
48GB_Mode input is strapped Low for 32 GB support over four ranks/channel. The
BIOS can read this bit to determine the mode of operation of the Intel
Memory Controller Hub Chipset.
Reserved
Reserved
(increment period x ((2^32)-1))
Maximum Period
Intel
Description
Description
206.2 s
257.7 s
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
Table 58
shows the
®
5100
July 2009