HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 15

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
Tables
July 2009
Order Number: 318378-005US
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PCI Express* Packet Visibility By Link Layer............................................................... 317
PCI Express* Packet Visibility By Transaction Layer .................................................... 320
Legacy Interrupt Routing (INTA Example) ................................................................. 336
Intel
Power-On Reset Sequence ...................................................................................... 346
Intel
DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled)....... 352
DWORD Configuration Write Protocol (SMBus Block Write, PEC Disabled)....................... 352
DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled) .............. 353
DWORD Memory Write Protocol................................................................................ 353
DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) ....... 353
DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled) ....................... 353
DWORD Memory Read Protocol (SMBus Word Write/Word Read, PEC Disabled) .............. 354
WORD Configuration Write Protocol (SMBus Byte Write, PEC Disabled) .......................... 354
SMBus Configuration Read (Block Write/Block Read, PEC Enabled)................................ 356
SMBus Configuration Read (Word Writes/Word Reads, PEC Enabled) ............................. 357
SMBus Configuration Read (Write Bytes/Read Bytes, PEC Enabled) ............................... 357
SMBus Configuration Write (Block Write, PEC Enabled)................................................ 358
SMBus Configuration Write (Word Writes, PEC Enabled) .............................................. 358
SMBus Configuration Write (Write Bytes, PEC Enabled) ............................................... 358
Random Byte Read Timing ...................................................................................... 359
Byte Write Register Timing ...................................................................................... 360
PCI Hot Plug*/VPP Block Diagram ............................................................................ 362
DDR Error Recovery Scheme ................................................................................... 376
Simplified TAP Controller Block Diagram.................................................................... 387
TAP Controller State Machine ................................................................................... 388
TAP Instruction Register.......................................................................................... 390
TAP Instruction Register Operation ........................................................................... 390
TAP Instruction Register Access ............................................................................... 391
TAP Data Register .................................................................................................. 392
Bypass Register Implementation .............................................................................. 393
Intel
Intel
Intel
Intel
Bottom View.......................................................................................................... 432
Top View .............................................................................................................. 433
Bottom View with Package Height ............................................................................ 434
Terminology ............................................................................................................ 23
Related Documents .................................................................................................. 29
Signal Naming Conventions ....................................................................................... 34
Buffer Signal Types .................................................................................................. 34
Processor Front Side Bus 0 Signals ............................................................................. 35
Processor Front Side Bus 1 Signals ............................................................................. 40
DDR2 Channel 0 Signals ........................................................................................... 44
DDR2 Channel 1 Signals ........................................................................................... 46
PCI Express* Common Signals................................................................................... 48
PCI Express* Port 0, Enterprise South Bridge Interface (ESI) Signals .............................. 49
PCI Express* Port 2 Signals ....................................................................................... 49
PCI Express* Port 3 Signals ....................................................................................... 49
PCI Express* Port 4 Signals ....................................................................................... 50
PCI Express* Port 5 Signals ....................................................................................... 50
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5100 Memory Controller Hub Chipset Power Sequencing .................................... 345
5100 Memory Controller Hub Chipset SMBus Interfaces ..................................... 347
5100 Memory Controller Hub Chipset Quadrant Map.......................................... 396
5100 Memory Controller Hub Chipset Ballout Left Side (Top View)....................... 397
5100 Memory Controller Hub Chipset Ballout Center (Top View).......................... 398
5100 Memory Controller Hub Chipset Ballout Right Side (Top View)..................... 399
5100 MCH Chipset
Intel
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5100 Memory Controller Hub Chipset
Datasheet
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