HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 344

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.19.1.2
5.19.1.3
5.19.1.4
Intel
Datasheet
344
®
5100 Memory Controller Hub Chipset
Hard Reset Mechanism
Once the Intel
may still be required to recover from system error conditions related to various device
or subsystem failures. The “hard” reset mechanism is provided to accomplish this
recovery without clearing the “sticky” error status bits useful to track down the cause of
system reboot.
A hard reset is typically initiated by the ICH9R component via the PLTRST# output pin,
which is commonly connected directly to the Intel
pin. The ICH9R may be caused to assert PLTRST# via both software and hardware
mechanisms. The Intel
RESETI# is asserted while PWRGOOD remains asserted.
The Intel
subordinate PCI Express* subsystems. The FSB components are reset via the FSB{0/
1}RESET# signals, while the PCI Express* subsystems are reset implicitly when the
root port links are taken down.
A hard reset will clear all internal state machines and logic, and initialize all “non-
sticky” registers to their default states. Note that although the error registers will
remain intact to facilitate root-cause of the hard reset, the Intel
based platform in general will require a full configuration and initialization sequence to
be brought back on-line.
Processor-Only Reset Mechanism
For power management and other reasons, the Intel
targeted processor only reset semantic. This mechanism was added to the platform
architecture to eliminate double-reset to the system when reset-signaled processor
information (such as clock gearing selection) must be updated during initialization
bringing the system back to the S0 state after power had been removed from the
processor complex.
Targeted Reset Mechanism
The targeted reset is provided for PCI Hot Plug* events, as well as for port-specific
error handling under Machine Check Architecture (MCA) or SMI software control. The
former usage model is new with PCI Express* technology, and the reader is referred to
the PCI Express* Base Specification, Rev. 1.0a for a description of the PCI Hot Plug*
mechanism.
A targeted reset may be requested by setting bit 6 (Secondary Bus Reset) of the Bridge
Control Register (offset 3Eh) in the target root port device. This reset will be identical
to a general hard reset from the perspective of the destination PCI Express* device; it
will not be differentiated at the next level down the hierarchy. Sticky error status will
survive in the destination device, but software will be required to fully configure the
port and all attached devices once reset and error interrogation have completed. After
clearing bit 6, software may determine when the downstream targeted reset has
effectively completed by monitoring the state of bit 1 (Link Active) of the VS_STS1
register (offset 47h) in the target root port device. This bit will remain deasserted until
the link has regained “link up” status, which implies that the downstream device has
completed any internal and downstream resets, and successfully completed a full
training sequence.
Under normal operating conditions it should not be necessary to initiate targeted resets
to downstream devices, but the mechanism is provided to recover from combinations
of fatal and uncorrectable errors which compromise continued link operation.
®
5100 MCH Chipset will propagate a hard reset to the FSB and to all
®
5100 MCH Chipset has been booted and configured, a full system reset
®
5100 MCH Chipset will recognize a hard reset any time
Intel
®
®
5100 MCH Chipset—Functional Description
5100 MCH Chipset RESETI# input
®
5100 MCH Chipset supports a
Order Number: 318378-005US
®
5100 MCH Chipset-
July 2009