HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 297

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.5.3
5.5.4
July 2009
Order Number: 318378-005US
While not recommended, agents can share interrupts to better utilize each interrupt
(implying level-triggered interrupts). Due to ordering constraints, agents can not use
an interrupt controller that resides on a different PCI bus. Therefore either only agents
on the same PCI bus can share interrupts, or the driver MUST follow the PCI
requirement that interrupt routines must first read the PCI interrupt register
The Intel
cycle for legacy 8259 support. These are routed to the compatibility ICH9R in the
system. The INTA will return data that provides the interrupt vector.
Message Signaled Interrupts
A second mechanism for devices to send interrupts is to issue the Message Signaled
Interrupt (MSI) introduced in the PCI Local Bus Specification, Rev. 2.3. This appears as
a 1 DWORD write on the PCI/PCI-X/PCI Express* bus.
With PCI devices, there are two types of MSIs. One type is where a PCI device issues
the inbound write to the interrupt range. The other type of MSI is where a PCI device
issues an inbound write to the upstream APIC controller (for example, in the Intel
6700PXH 64-bit PCI Hub) where the APIC controller converts it into an inbound write to
the interrupt range. The second type of MSI can be used in the event the OS doesn’t
support MSIs, but the BIOS does. In either way, the interrupt will appear as an inbound
write to the Intel
MSI is expected to be supported by the operating systems when the Intel
Chipset is available. A Intel
mechanism in the event that there is a short period of time when MSI is not available.
This is described in
Non-MSI Interrupts - “Fake MSI”
For interrupts coming through the Intel
components, their APIC controller will convert interrupts into inbound writes, so
inbound interrupts will appear in the same format as an MSI.
For interrupts that are not coming through an APIC controller, it is still required that the
interrupt appear as an MSI-like interrupt. If the OS does not yet support MSI, the PCI
Express* device can be programmed by the BIOS to issue inbound MSI interrupts to an
IOxAPIC in the system. The safest IOxAPIC to choose would be the ICH9R since it is
always present in a system. Although the Intel
Express* “Assert_INT” and “Deassert_INT” packets for boot, the performance is not
optimal and is not recommended for run time interrupts.
In this method, PCI Express* devices are programmed to enable MSI functionality, and
given a write path directly to the pin assertion register in a selected IOxAPIC already
present in the platform. The IOxAPIC will generate an interrupt message in response,
thus providing equivalent functionality to a virtual (edge-triggered) wire between the
PCI Express* endpoint and the I/OxAPIC.
All PCI Express* devices are strictly required to support MSI. When MSI is enabled, PCI
Express* devices generate a memory transaction with an address equal to the I/
OxAPIC_MEM_BAR + 20 and a 32-bit data equal to the interrupt vector number
corresponding to the device. This information is stored in the device’s MSI address and
data registers, and would be initialized by the system firmware (BIOS) prior to booting
a non-MSI aware operating system. (With the theory that an MSI aware O/S would
then over-write the registers to provide interrupt message delivery directly from the
endpoint to the CPU complex.)
®
®
5100 MCH Chipset supports the INTA (interrupt acknowledge) special bus
5100 MCH Chipset
®
5100 MCH Chipset over the PCI Express* ports.
Section 5.5.4, “Non-MSI Interrupts - “Fake MSI”.”
®
5100 MCH Chipset will also feature a backup interrupt
®
6700PXH 64-bit PCI Hub and ICH9R
®
5100 MCH Chipset supports the PCI
Intel
®
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
®
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