HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 72
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
Lead Free Status / RoHS Status
Compliant
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Table 27.
3.4.1
Table 28.
Intel
Datasheet
72
CPU/Inbound CB_BAR
MMIO Access
CFGADR Register
CFC on FSB
SMBus Config Access
Fixed MCH Memory
Mapped on FSB
MCH Register Decoding
Component
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
MCH
®
5100 Memory Controller Hub Chipset
ESI Port (Port 0)
PCI Express* Port 2
PCI Express* Port 3
PCI Express* Port 4
PCI Express* Port 5
PCI Express* Port 6
PCI Express* Port 7
DMA Engine
DMA Engine MMIO Space
Miscellaneous Registers.
Memory Map, Error Flag/Mask,
RAS, Channel 0 Control
Memory Map, Error Flag/Mask,
RAS, Channel 1 Control
Processor Bus, Boot, Interrupt,
System Address
Configuration Address Bit Mapping (Sheet 2 of 2)
Special Device and Function Routing
All devices in the Intel
Specially Handled by Intel® 5100 Memory Controller Hub Chipset”
devices and functions that the MCH implements or routes specially.
Functions Specially Handled by Intel
(Sheet 1 of 2)
Register Group
Source
Source
Source
Source
Source
Destination
Destination
Source/
0
Bus[7:0]
CFGADR
Bus[7:0]
0
00000000
®
Bus
5100 MCH Chipset reside on Bus 0.
65C0h
65E2h
65E3h
65E4h
65E5h
65E6h
65E7h
65FFh
N/A
65F3h
65F5h
65F6h
65F0h
Register—see row above
DID
8
Dev[4:0]
Dev[4:0]
16
See
Table 28,
“Functions
Specially
Handled by
Intel®
5100
Memory
Controller
Hub
Chipset.”
Device
0
2
3
4
5
6
7
8
8
19
21
22
16
Device
®
Function
1
Func[2:0]
Func[2:0]
0
Func[2:0]
5100 Memory Controller Hub Chipset
Function
0
0
0
0
0
0
0
0
1
0
0
0
0
Intel
®
A[11:8]
Not
present
Reg[11:8]
Cannot
access
DW
Offset[9:6]
5100 MCH Chipset—Register Description
[11:8]
Depending on what is connected to these
ports, some may not be accessible.
Device mapping for DMA Engine
Debug in higher address offsets.
Debug in higher address offsets.
Debug in higher address offsets.
DW Offset
Table 28, “Functions
A[7:3]
BE[7:4]
Reg[5:0]
Reg[7:2]
A[15:10]
DW
Offset[5:0]
Order Number: 318378-005US
[5:0]
Comment
describes the
BE[7:0]
Not
present
BE[7:4]
Command,
Register
Number
All
accesses
are 4-byte
Byte[3:0]
Byte in
DW
July 2009
Type
N/A
N/A
N/A
N/A
N/A
N/A
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