HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 152

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.11.11
Intel
Datasheet
152
®
5100 Memory Controller Hub Chipset
PEXSLOTSTS[7:2, 0] - PCI Express* Slot Status Register
The PCI Express* Slot Status register defines important status information for
operations such as PCI Hot Plug* and Power Management.
Device:
Function:
Offset:
Device:
Function:
Offset:
15:7
Bit
Bit
2
1
0
6
5
4
RWC
Attr
Attr
RW
RW
RW
RO
RO
RV
0, 2-3, 4-7
0
84h
0, 2-3, 4-7
0
86h
Default
Default
0h
0h
0h
0h
1h
0h
0h
MRLINTEN: MRL Sensor Changed Enable
Always write to ‘0’, the Intel
Plug* capability.
This bit enables the generation of PCI Hot Plug* interrupts or wake messages
via a MRL Sensor changed event.
0: Disables generation of PCI Hot Plug* interrupts or wake messages when an
MRL Sensor changed event happens.
1: Enables generation of PCI Hot Plug* interrupts or wake messages when an
MRL Sensor changed event happens.
PWRINTEN: Power Fault Detected Enable
Always write to ‘0’, the Intel
Plug* capability.
This bit enables the generation of PCI Hot Plug* interrupts or wake messages
via a power fault event.
0: Disables generation of PCI Hot Plug* interrupts or wake messages when a
power fault event happens.
1: Enables generation of PCI Hot Plug* interrupts or wake messages when a
power fault event happens.
ATNINTEN: Attention Button Pressed Enable
Always write to ‘0’, the Intel
Plug* capability.
This bit enables the generation of PCI Hot Plug* interrupts or wake messages
via an attention button pressed event.
0: Disables generation of PCI Hot Plug* interrupts or wake messages when the
attention button is pressed.
1: Enables generation of PCI Hot Plug* interrupts or wake messages when the
attention button is pressed.
Reserved.
PDS: Presence Detect State
This field conveys the Presence Detect status determined via an in-band
mechanism or through the Present Detect pins and shows the presence of a
card in the slot.
0: Slot Empty
1: Card Present in slot
MRLSS: MRL Sensor State
This bit reports the status of an MRL sensor if it is implemented.
0: MRL Closed
1: MRL Open
CMDCMP: Command Completed
This bit is set by the Intel
controller completes an issued command and is ready to accept a new
command. It is subsequently cleared by software after the field has been read
and processed.
®
Intel
®
®
®
5100 MCH Chipset when the PCI Hot Plug*
5100 MCH Chipset does not support PCI Hot
5100 MCH Chipset does not support PCI Hot
5100 MCH Chipset does not support PCI Hot
®
Description
Description
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009