HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 58

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Figure 3.
Intel
Datasheet
58
®
5100 Memory Controller Hub Chipset
Intel
®
x16
5100 Memory Controller Hub Chipset Signal Diagram 48 GB Mode
x8
x8
x8
x4
PEICOM PI, PERCOM PO
x4
x4
x4
x4
x4
x4
(ESI) PE0R{P/N}[3:0]
(ESI) PE0T{P/N}[3:0]
SPD0SM BDATA
PE2R{P/N}[3:0]
PE2T{P/N}[3:0]
PE3R{P/N}[3:0]
PE3T{P/N}[3:0]
PE4R{P/N}[3:0]
PE4T{P/N}[3:0]
PE5R{P/N}[3:0]
PE5T{P/N}[3:0]
PE6R{P/N}[3:0]
PE6T{P/N}[3:0]
PE7R{P/N}[3:0]
PE7T{P/N}[3:0]
GPIOSM BDA TA
XDPSTB{P/N}#
TDIOCATHODE
CORECLK{P/N}
PEW IDTH[3:0]
CFGSM BDA TA
XDPCOM CRES
XDPODTCRES
XDPSLW CRES
SPD0SM BCLK
FSBODTCRES
FSBSLW CRES
FSBSLW CTRL
XDPD[15:0]#
GPIOSM BCLK
A SYNCRFSH
CFGSM BCLK
TDIOANODE
PECLK{P/N}
COREVCCA
COREVSSA
FSB0VREF
FSB1VREF
PW RGOOD
ERR[2:0]#
XDPRDY#
PSEL[2:0]
PEVCCBG
PEVSSBG
FSBVCCA
FSBCRES
RESETI#
VCCDDR
PEVCCA
PEVSSA
TRST#
V3REF
VCCPE
RSVD
TDO
TM S
VTT
TCK
VCC
VSS
TDI
Express*
Interfaces
XD Port
Ground
Intel® 5100 MCH Chipset
SMBus
Pow er
Reset
Clock
JTAG
Misc
Bus
PCI
Channel 0
Channel 1
Bus 0
Bus 1
DDR2
DDR2
Front
Front
Side
Side
Intel
FSB0A[35:3]
FSB0ADSTB[1:0]#, FSB0ADS#
FSB0AP[1:0]#
FSB0BINIT#, FSB0BNR#
FSB0BPM [5:4]#
FSB0BPRI#
FSB0BREQ[1:0]#
FSB0D[63:0]#
FSB0DBI[3:0]#
FSB0DBSY#, FSB0DRDY#
FSB0DEFER#
FSB0DP[3:0]#
FSB0DSTB{P/N}[3:0]#
FSB0HIT#, FSB0HITM #
FSB0LOCK#
FSB0M CERR#
FSB0REQ[4:0]#
FSB0RESET#
FSB0RS[2:0]#
FSB0RSP#, FSB0TRDY#
FSB1A[35:3]
FSB1ADSTB[1:0]#, FSB1ADS#
FSB1AP[1:0]#
FSB1BINIT#, FSB1BNR#
FSB1BPM [5:4]#
FSB1BPRI#
FSB1BREQ[1:0]#
FSB1D[63:0]#
FSB1DBI[3:0]#
FSB1DBSY#, FSB1DRDY#
FSB1DEFER#
FSB1DP[3:0]#
FSB1DSTB{P/N}[3:0]#
FSB1HIT#, FSB1HITM #
FSB1LOCK#
FSB1M CERR#
FSB1REQ[4:0]#
FSB1RESET#
FSB1RS[2:0]#
FSB1RSP#, FSB1TRDY#
CH0_DQ[63:0]
CH0_DQS{P/N}[17:0]
CH0_CB[7:0]
CH0_A[14:0]
CH0_BA[2:0]
CH0_CAS#
CH0_RAS#
CH0_W E#
CH0_CS[5:0]#
CH0_CKE[2:0]
CH0_ODT[5:0]
CH0_DCLK{P/N}[2:0]
CH0_CRES{1/2}, CH0_CRESRET
CH0_DRVCRES, CH0_SLEW CRES
48GB_M ode
CH1_DQ[63:0]
CH1_DQS{P/N}[17:0]
CH1_CB[7:0]
CH1_A[14:0]
CH1_BA[2:0]
CH1_CAS#
CH1_RAS#
CH1_W E#
CH1_CS[5:0]#
CH1_CKE[2:0]
CH1_ODT[5:0]
CH1_DCLK{P/N}[2:0]
CH1_CRES{1/2}, CH1_CRESRET
CH1_DRVCRES, CH1_SLEW CRES
®
5100 MCH Chipset—Signal Description
Data
Com m and/
Address
Control
Clock
Data
Com m and/
A ddress
Control
Clock
Order Number: 318378-005US
July 2009