HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 231

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.11.15
3.11.16
3.11.17
3.11.18
July 2009
Order Number: 318378-005US
PEXCAPID: PCI Express* Capability ID Register
PEXNPTR: PCI Express* Next Pointer Register
PEXCAP - PCI Express* Capabilities Register
PEXDEVCAP - Device Capabilities Register
Device:
Function:
Offset:
7:0
Device:
Function:
Offset:
7:0
Device:
Function:
Offset:
15:14
13:9
8
7:4
3:0
Device:
Function:
Offset:
31:28
27:26
Bit
Bit
Bit
Bit
RO
RO
RV
RO
RO
RO
RO
RV
RO
Attr
Attr
Attr
Attr
®
5100 MCH Chipset
8
0
6Ch
8
0
6Dh
8
0
6Eh
8
0
70h
10h
00h
0h
0h
0
1001
0001
0h
00
Default
Default
Default
Default
CAPID: PCI Express* Capability ID
This code denotes the standard PCI Express* capability.
NXTPTR: PCI Express* Next Pointer
The PCI Express* capability structure is the last capability in the linked list and set
to NULL.
Reserved
IMN: Interrupt Message Number:
This field indicates the interrupt message number that is generated from the DMA
Engine device. When there are more than one MSI interrupt Number, this register
field is required to contain the offset between the base Message Data and the MSI
Message that is generated when the status bits in the slot status register or root
port status registers are set.
Slot_Impl: Slot Implemented: DMA Engine is an integrated device and therefore a
slot is never implemented.
DPT: Device/Port Type: DMA Engine device represents a PCI Express* Endpoint.
VERS: Capability Version: DMA Engine supports PCI Express* Base Specification,
Rev. 1.0a.
Reserved
CSPLS: Captured Slot Power Limit Scale
This field applies only to upstream ports. Hardwired to 0h
Description
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
231