HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 271

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
Table 82.
July 2009
Order Number: 318378-005US
Address Disposition for Processor (Sheet 1 of 2)
DOS
SMM/VGA
C and D BIOS
segments
E and F BIOS
segments
Low/Medium
Memory
Extended
SMRAM Space
Low MMIO
PCI Express*
MMCFG
Intel
MCH Chipset-
specific
I/O APIC
registers
ICH9R/ICH9R
timers
Address Range
®
5100
®
5100 MCH Chipset
0 to 09FFFFh
0A0000h to 0BFFFFh
0C0000h to 0DFFFFh and PAM=11
Write to
0C0000h to 0DFFFFh and PAM=10
Read to
0C0000h to 0DFFFFh and PAM=01
Read to
0C0000h to 0DFFFFh and PAM=10
Write to
0C0000h to 0DFFFFh and PAM=01
0C0000h to 0DFFFFh and PAM=00
0E0000h to 0FFFFFh and PAM=11
Write to
0E0000h to 0FFFFFh and PAM=10
Read to
0E0000h to 0FFFFFh and PAM=01
Read to
0E0000h to 0FFFFFh and PAM=10
Write to
0E0000h to 0FFFFFh and PAM=01
0E0000h to 0FFFFFh and PAM=00
10_0000 <= Addr < TOLM
ESMMTOP-TSEG_SZ <= Addr <
ESMMTOP
TOLM <= Addr < FE00_0000 and
falls into a legal BASE/LIMIT range
TOLM <= Addr < FE00_0000 and
not in a legal BASE/LIMIT range
HECBASE <= Addr <
HECBASE+256 MB
FE00_0000h to FEBF_FFFFh AND
valid Intel
memory mapped register address
FE00_0000h to FEBF_FFFFh AND
(NOT a valid Intel
Chipset memory mapped register
address)
FEC0_0000 to FEC8_FFFFh
FEC9_0000h to FED1_FFFF
®
Conditions
5100 MCH Chipset
®
5100 MCH
Coherent Request to Main Memory. Route to main
memory according to SC.MIR registers. Apply
Coherence Protocol.
See
from Processor”
Requests to SMM and VGA Spaces.”
Non-coherent request to main memory. Route to
appropriate DDR2 DIMM device according to SC.MIR
registers.
Issue request to ESI.
Non-coherent request to main memory. Route to
appropriate DDR2 DIMM device according to SC.MIR
registers.
Issue request to ESI.
Coherent request to main memory. Route to main
memory according to SC.MIR registers. Coherence
protocol is applied.
Note:
See
from Processor”
Requests to SMM and VGA Spaces.”
Request to PCI Express* based on <MBASE/MLIMIT
and PMBASE/PMLIMIT> registers.
Send to ESI to be master aborted.
Convert to a configuration access and route
according to the Configuration Access Disposition.
Issue configuration access to memory mapped
register inside the Intel
DIMM based on the context.
Send to ESI to be master aborted.
Non-coherent request to PCI Express* or ESI based
on
Issue request to ESI.
Table 80, “I/O APIC Address Mapping.”
Table 84, “SMM Memory Region Access Control
Table 84, “SMM Memory Region Access Control
Intel
The extended SMRAM space is within this
range.
Intel
®
5100 MCH Chipset Behavior
®
and
and
5100 Memory Controller Hub Chipset
Table 85, “Decoding Processor
Table 85, “Decoding Processor
®
5100 MCH Chipset or to the
Datasheet
271