HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 304

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.10
Figure 22.
Intel
Datasheet
304
®
5100 Memory Controller Hub Chipset
Interrupt Swizzling
The Intel
inbound PCI Express* interrupts for performance and load balancing considerations.
Register INTxSWZCTRL[7:2,0] described in
PCI Express* Interrupt Swizzle Control Register”
swizzle the PCI Express* interrupt (INTx) from each PCI Express* port and remap them
to a different interrupt pin.
INTA (as depicted in
reserved per the PCI/PCI Express* specification for PCI/PCI Express* devices (if the
device uses interrupts), so it is of particular concern.
depicts interrupt swizzling where INTx is distributed.
examples of interrupt swizzling and are only used for illustration purposes, as system
board interrupt routing is platform-specific.
For optimal system performance, it is recommended that the system BIOS utilizes the
INTXSWZCTRL[7:2,0] register to achieve a more balanced PCI Express* interrupt
distribution. Note that the PCI interrupt routing table in the system BIOS needs to be
modified to match the particular swizzling scheme required for the specific system
design.
Interrupt Swizzle
®
5100 MCH Chipset has interrupt swizzling logic to rebalance and distribute
Figure 23, “No Interrupt
Section 3.8.8.35, “INTXSWZCTRL[7:2,0]:
Intel
Swizzle”) is usually overloaded since it is
®
provides software/BIOS the ability to
5100 MCH Chipset—Functional Description
Figure 22
Figure 22, “Interrupt Swizzle”
Order Number: 318378-005US
and
Figure 23
depict
July 2009