HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 269

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

System Address Map—Intel
4.3.8.2
4.3.8.3
4.3.8.4
4.3.9
4.3.9.1
4.3.9.2
4.4
July 2009
Order Number: 318378-005US
High MMIO
The high memory mapped I/O region is located above the top of memory as defined by
SC.MIR.LIMIT. These SC.PMBU and SC.PMLU registers in each PCI Express*
configuration device determine whether there is memory mapped I/O space above the
top of memory. If an access is above MIR.LIMIT and it falls within the
SC.PMBU+PMBASE and SC.PMLU+PMLIMIT range, it should be routed to the
appropriate PCI Express* port. For accesses above MIR.LIMIT (and above 4 GB) that
are not in a high MMIO region, they should be master aborted.
CB_BAR MMIO
The integrated DMA device has a 1 kB MMIO space with a default range from FE70
0000h to FE70 03FFh. This range can be relocated by programming CB_BAR register.
This range could be used as a private MMIO space by software.
Extended Memory
The range of memory just below 4 GB from TOLM to 4 GB (Low MMIO, Chipset,
Interrupt/SMM/LT) does not map to memory. If the DRAM memory, behind the TOLM to
4 GB range, is not relocated, it will be unused.
The Intel
Note that ESMMTOP cannot be greater than TOLM.
Main Memory Region
Application of Coherency Protocol
The Intel
memory. Application of the coherency protocol includes snooping the other processor
bus.
Two exceptions to this rule are the Expansion Card BIOS area, 0C 0000h - 0F FFFFh
and the legacy SMM, 0A 0000h - 0B FFFFh, range. The Expansion Card BIOS area 0C
0000h - 0F FFFFh may not necessarily route both reads and writes to memory, the
legacy SMM range, 0A 0000h - 0B FFFFh, may target non-memory when not in SMM
mode. The coherency protocol is not applied to these two exceptions.
Routing Memory Requests
When a request appears on the processor bus, ESI port, or PCI Express* link, and it
does not fall in any of the previously mentioned regions, it is compared against the
MIR.LIMIT registers in the MCH.
The SC.MIR.LIMIT registers will decode an access into a specific interleaving range.
Within the interleaving range, the SC.MIR.LIMIT register indicates which DDR2 memory
channel the address is associated with.
Memory Address Disposition
The following section presents a summary of address dispositions for the Intel
MCH Chipset.
®
®
®
5100 MCH Chipset
5100 MCH Chipset uses MIR.LIMIT to indicate the top of usable memory.
5100 MCH Chipset applies the coherency protocol to all accesses to main
Intel
®
5100 Memory Controller Hub Chipset
®
Datasheet
5100
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