HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 348

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.20.1
5.20.2
Intel
Datasheet
348
®
5100 Memory Controller Hub Chipset
Internal Access Mechanism
All SMBus accesses to internal register space are initiated via a write to the CMD byte.
Any register writes received by the MCH while a command is already in progress will
receive a NAK to prevent spurious operation. The master is no longer expected to poll
the CMD byte to prevent the obliteration a command in progress prior to issuing further
writes. The SMBus access will be delayed by stretching the clock until such time that
the data is delivered. Note that per the System Management Bus (SMBus)
Specification, Version 2.0, this can not be longer than 25 ms. To set up an internal
access, the four ADDR bytes are programmed followed by a command indicator to
execute a read or write. Depending on the type of access, these four bytes indicate
either the Bus Number, Device, Function, Extended Register Offset, and Register Offset,
or the memory-mapped region selected and the address within the region. The
configuration type access utilizes the traditional bus number, device, function, and
register offset; but in addition, also uses an extended register offset which expands the
addressable register space from 256 bytes to 4 kB. The memory-mapped type access
redefines these bytes to be a memory-mapped region selection byte, a filler byte which
is all zeroes, and then the memory address within the region, see the below SMBus
descriptions. Note that the filler byte is not utilized, but enforces that both types of
accesses have the same number of address bytes, and does allow for future expansion.
It is perfectly legal for an SMBus access to be requested while an FSB-initiated access
is already in progress. The MCH supports “wait your turn” arbitration to resolve all
collisions and overlaps, such that the access that reaches the configuration ring arbiter
first will be serviced first while the conflicting access is held off. An absolute tie at the
arbiter will be resolved in favor of the FSB. Note that SMBus accesses must be allowed
to proceed even if the internal MCH transaction handling hardware and one or more of
the other external MCH interfaces are hung or otherwise unresponsive.
SMBus and PCI Express* Interoperability Timeout
Recommendation
The System Management Bus (SMBus) Specification, Version 2.0, Section 3.1.1, SMBus
Common AC Specifications, states the timeout value to be 25 ms and the PCI Express*
Base Specification, Rev. 1.0a, Section 2.8, Completion Timeout Mechanism, specifies
PCI Express* global timeout of 50 ms. Due to Erratum 22, SMBus TLOW:SEXT
specification may be exceeded on SMBus 0 when the north bridge is clocked with a 266
MHz BUSCLK, once a timeout occurs, SMBus hangs until a hard reset. Any SMBus
transaction through the Intel
Intel
hang. Please refer to Intel
for details on Erratum 22.
Intel recommends that the PCI Express* Global Control Register (PEXGCTRL)
Completion Timeout be programmed to less than the SMBus timeout. Currently, Intel
sets the timeout to approximately 20 ms (Completion timeout register value = 744h) in
the BIOS. For a more detailed description of the PEXGCTRL register, please refer to
Section 3.8.8.34, “PEXGCTRL - PCI Express* Global Control Register.”
5100 MCH Chipset-based system to encounter this error (SMBus hang), two conditions
must be met. One, the Intel
PEXGCTRL Completion Timeout value greater than 25 ms. Two, an SMBus master on
the Intel
Express* device through the MCH; then, if this operation takes more than 25 ms, the
SMBus will hang. It is important to note that an SMBus master reading from the Intel
5100 MCH Chipset (Bus 0) will not encounter the SMBus hang. Systems that do not
access any SMBus devices outside of the Intel
5100 MCH Chipset can safely set the timeout value to 50 ms to conform to the PCI
Express* Base Specification, Rev. 1.0a. There is no planned fix for this.
®
5100 MCH Chipset taking longer than 25 ms to complete will cause the SMBus to
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5100 MCH Chipset-based system would have to read data from a PCI or PCI
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®
5100 Memory Controller Hub Chipset Specification Update
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5100 MCH Chipset-based system would need to have a
5100 MCH Chipset targeting any device outside of the
Intel
®
5100 MCH Chipset through the Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
For an Intel
July 2009
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