HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 40

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.1.2
Table 6.
Intel
Datasheet
40
®
5100 Memory Controller Hub Chipset
Processor Front Side Bus 1
Processor Front Side Bus 1 Signals (Sheet 1 of 4)
FSB1A[35:3]#
FSB1ADS#
FSB1ADSTB[1:0]#
FSB1AP[1:0]#
FSB1BINIT#
Signal Name
I/O
I/O
I/O
I/O
I/O
Type
Processor 1 Address Bus:
FSB1A[35:3]# define a 2
1 of the address phase, these signals transmit the address of a transaction. In
sub-phase 2, these signals transmit transaction type information.
FSB1A[35:3]# are protected by parity signals FSB1AP[1:0]#. FSB1A[35:3]#
are source synchronous signals and are latched into the receiving buffers by
FSB1ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset
of the FSB1A[35:3]# lands to determine their power-on configuration.
FSB1A[35:3]# connect to the processor address bus. During processor cycles,
FSB1A[35:3]# are inputs. The MCH drives FSB1A[35:3]# during snoop cycles
on behalf of ESI and Secondary PCI initiators. FSB1A[35:3]# are transferred at
2x rate. Note that the address is inverted on the processor bus.
Processor 1 Address Strobe:
FSB1ADS# is asserted to indicate the validity of the transaction address on
FSB1A[35:3]#. All bus agents observe the FSB1ADS# activation to begin parity
checking, protocol checking, address decode, internal snoop, or deferred reply
ID match operations associated with the new transaction. The processor bus
owner asserts FSB1ADS# to indicate the first of two cycles of a request phase.
Processor 1 Address Strobe:
FSB1ADSTB[1:0]# are source synchronous strobes used to transfer
FSB1A[35:3]# and FSB1REQ[4:0]# at the 2x transfer rate on the strobes rising
and falling edges.
Processor 1 Address Parity:
FSB1AP[1:0]# provide parity protection on the address bus. FSB1AP[1:0]# are
driven by the request initiator along with FSB1ADS#, FSB1A[35:3]#, and the
transaction type on the FSB1REQ[4:0]# signals. A correct parity signal is high if
an even number of covered signals are low and low if an odd number of covered
signals are low. This allows parity to be high when all the covered signals are
high. The following defines the coverage model of these signals.
Processor 1 Bus Initialization:
FSB1BINIT# may be observed and driven by all processor FSB agents. If the
FSB1BINIT# driver is enabled during power on configuration, FSB1BINIT# is
asserted to signal any bus condition that prevents reliable future operation.
If FSB1BINIT# observation is enabled during power-on configuration and
FSB1BINIT# is sampled asserted, symmetric agents reset their bus LOCK#
activity and bus request arbitration state machines. The bus agents do not
reset their I/O Queue (IOQ) and transaction tracking state machines upon
observation of FSB1BINIT# assertion. Once the FSB1BINIT# assertion has
been observed, the bus agents will re-arbitrate for the FSB and attempt
completion of their bus queue and IOQ entries.
If FSB1BINIT# observation is disabled during power-on configuration, a priority
agent may handle an assertion of FSB1BINIT# as appropriate to the error
handling architecture of the system.
Request Signals
FSB1REQ[4:0]#
FSB1A[35:24]#
FSB1A[23:3]#
FSB1A[35:17]#
FSB1REQ[4:0],
FSB1A[16:3]#
Signals
36
Subphase 1
FSB1AP[0]#
FSB1AP[1]#
FSB1AP[1]#
-byte physical memory address space. In sub-phase
Associated Strobes
Intel
FSB1ADSTB[0]#
FSB1ADSTB[1]#
Description
®
5100 MCH Chipset—Signal Description
Subphase 2
FSB1AP[1]#
FSB1AP[0]#
FSB1AP[0]#
Order Number: 318378-005US
July 2009