HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 234

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.11.21
3.11.21.1
Intel
Datasheet
234
®
5100 Memory Controller Hub Chipset
DMA Error Logging
The following error registers record the occurrence of the first and next errors of the
DMA Engine along with the necessary debug information based on the context.
CB_ERR_DOCMD - DMA Engine Error Do Command Register
Device:
Function:
Offset:
5
4
3
2
1
0
Device:
Function:
Offset:
Bit
31:2
1:0
Bit
RO
RO
RO
RWC
RWC
RWC
Attr
RWST
Attr
RV
8
0
76h
8
0
7Ch
0
0
0
0
0
0
Default
Default
0h
00
TP: Transactions Pending
This bit indicates that the DMA Engine device has issued non-posted PCI Express*
transactions which have not yet completed.
Note that the Intel
transactions and hence this is hardwired to zero.
APD: AUX Power Detected
The DMA Engine device does not support AUX power. Hardwired to 0h.
URD: Unsupported Request Detected
This does not apply to DMA Engine in the Intel
messages for the DMA Engine. Hardwired to 0h
FED: Fatal Error Detected
This bit gets set if a fatal uncorrectable error is detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in the Device
Control register. (See FERE in
Register.”)
1: Fatal errors detected
0: No Fatal errors detected
NFED: Non-Fatal Error Detected
This bit gets set if a non-fatal uncorrectable error is detected.
Errors are logged in this register regardless of whether error reporting is enabled or
not in the Device Control register. (See NFERE in
Device Control
1: Non Fatal errors detected
0: No non-Fatal Errors detected
CED: Correctable Error Detected
This bit gets set if a correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register. (See CERE in
1: correctable errors detected
0: No correctable errors detected
Reserved.
CB_FAT_MAP: DMA Engine steering for fatal errors
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
The CB Fatal errors are routed to one of the ERR[2:0] pins or MCERR.
Register.”)
®
5100 MCH Chipset DMA Engine device does not issue any NP
Section 3.11.19, “PEXDEVCTRL - Device Control
Section 3.11.19, “PEXDEVCTRL - Device Control
Intel
Description
®
5100 MCH Chipset—Register Description
Description
®
5100 MCH Chipset as there are no
Section 3.11.19, “PEXDEVCTRL -
Order Number: 318378-005US
Register.”)
July 2009