HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 111

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 52.
July 2009
Order Number: 318378-005US
Accessibility of the Intel
Device
Figure 12, “PCI Express* Configuration Space”
configuration space appears to software. Each PCI Express* port’s configuration space
has four regions:
PCI Express*
• Standard PCI Header - This region closely resembles a standard PCI-to-PCI
• PCI Device Dependent Region - The region is also part of standard PCI
• PCI Express* Extended Configuration Space - This space is an enhancement
• Capability Working Register Sets - These ranges are indirectly accessed
bridge header.
configuration space and contains the PCI capability structures. For the Intel
MCH Chipset, the supported capabilities are:
beyond standard PCI and only accessible with PCI Express* aware software. The
MCH supports the Enhanced Error Signaling capability.
through Data and Select registers in the capability structures. For the MCH,
working register sets exist for the Standard PCI Hot Plug* Controller and Power
Management capabilities.
Port
— Message Signaled Interrupts
— PCI Hot Plug*
— PCI Express* Capability
7
6
5
4
3
2
0
®
5100 MCH Chipset
Device
7
6
5
4
3
2
0
possible
combination
possible
combination
possible
combination
ESI - Not
combinable
®
x8
5100 Memory Controller Hub Chipset PCI Express*
Port 7 is connected to a x4 device
Port 6 is connected to a x4 or x8 device
Port 5 is connected to a 4x device
Port 4 is connected to a x4, x8 or x16 device
Port 3 is connected to a 4x device
Port 2 is connected to a x4 or x8 device
Port0 is connected to a x4 ICH9R port through ESI and cannot be
combined with any other port
illustrates how each PCI Express* port’s
Registers may be accessed if:
Intel
®
5100 Memory Controller Hub Chipset
®
Datasheet
5100
111