HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 48

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 8.
2.3
2.3.1
Table 9.
2.3.2
Intel
Datasheet
48
®
5100 Memory Controller Hub Chipset
DDR2 Channel 1 Signals (Sheet 3 of 3)
PCI Express* Signal List
PCI Express* Common Signals
PCI Express* Common Signals
PCI Express* Port 0, Enterprise South Bridge Interface (ESI)
PCI Express* port 0 is a x4 port dedicated to providing the ESI link between the Intel
5100 MCH Chipset and the ICH9R.
PECLKN
PECLKP
PEICOMPI
PERCOMPO
PEVCCA
PEVCCBG
PEVSSA
PEVSSBG
PEWIDTH[3:0]
CH1_SLEWCRES
CH1_ODT[5:4]
CH1_ODT[3:0]
Signal Name
CH1_RAS#
CH1_WE#
Name
Power/
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Other
Type
Type
O
O
O
O
I
Memory Channel 1 On Die Termination (Bits 5:4):
When 48GB_Mode is strapped High, these signals in addition to CH1_ODT[3:0]
operate as the dynamic on die termination enables for each of up to six ranks
on channel 1, where CH1_ODT[0] is for the first rank and CH1_ODT[5] is for
the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH1_CKE[3] and
CH1_A[15], respectively.
Memory Channel 1 On Die Termination (Bits 3:0):
When 48GB_Mode is strapped High, these signals in addition to CH1_ODT[5:4]
operate as the dynamic on die termination enables for each of up to six ranks
on channel 1, where CH1_ODT[0] is for the first rank and CH1_ODT[5] is for
the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH1_CKE[3] and
CH1_A[15], respectively.
Memory Channel 1 Row Address Strobe:
Used in write and pre-charge operations of DRAM. Specifies the SDRAM
command in combination with CH1_CS#, CH1_CAS# and CH1_WE#.
Memory Channel 1 Slew rate/DDR2_VTT Sense pin:
Connects to an external reference resistor to generate an internal bias which
controls the slew rate of the drivers.
Memory Channel 1 Write enable:
Used in write and pre-charge operations of DRAM. Specifies the SDRAM
command in combination with CH1_CS#, CH1_CAS# and CH1_RAS#.
PCI Express* Common Clock Negative Phase:
PCI Express* Common Clock Positive Phase:
PCI Express* Impedance Compensation:
PCI Express* Impedance Compensation:
PCI Express* VCC:
Analog Voltage for the PCI Express* PLL
PCI Express* Band Gap VCC:
Band Gap Voltage
PCI Express* VSS:
Analog Voltage for PCI Express* PLL
PCI Express* Band Gap VSS:
Band Gap Voltage
PCI Express* Port Width Strapping Pins:
Intel
Description
Description
®
5100 MCH Chipset—Signal Description
Order Number: 318378-005US
July 2009
®