HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 321

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Note:
5.14
5.14.1
July 2009
Order Number: 318378-005US
The Hardware Model is obsolete and no longer supported.
Engine Technology”
software model works and specifies requirements on BIOS, the OS, the DMA Engine
device driver, and the client for initializing, configuring, managing, and programming
the DMA Engine hardware.
The term “DMA Engine device driver” refers to an OS based device driver that is loaded
to control the DMA Engine device and the term “I/O device driver” or “client” refers to
an OS based device driver that is loaded to control a client I/O device (which might be
a DMA Engine client, i.e., the controlling process). Client access is always via the DMA
Engine driver, thus stating the client writes a register implies that the client passes the
request to the DMA Engine driver, which sets the register.
Using DMA Engine Technology
This section explains the mechanism by which software can request the use of and
configure DMA Engine technology capabilities.
High Level Requirements
A generic mechanism to expose DMA Engine capabilities to clients in an operating
system environment should meet the following high-level requirements:
Given these high-level requirements, a DMA Engine usage model must support a
startup and tear-down sequence that allows these requirements to be met. Thus, any
client of DMA Engine facilities must be able to:
1. It must support a single client using either a subset or all of DMA Engine features at
2. It must support multiple simultaneous clients, each using a subset or all of DMA
3. It must support DMA Engine capabilities to be dynamically requested and released.
4. It must support DMA Engine capabilities in a manner that is compatible with the
5. It must be flexible, such that it allows different DMA Engine implementations (e.g.,
6. It must be able to support a DMA Engine implementation that is “asymmetric” -
1. Detect the presence, version, & capabilities of DMA Engine technology that exists
2. Arbitrate for and reserve DMA Engine resources (e.g., DMA channels and Stream
3. Release DMA Engine resources (e.g., DMA channels and Stream Priority) when they
4. Manage plug and play and power management events that cause the client I/O
any given time.
Engine features as long as the simultaneous use is non-conflicting.
This can happen as client I/O devices are dynamically inserted and removed or the
device driver stack for client I/O devices is dynamically loaded and unloaded.
host operating system. For example, the mechanism must work correctly when
plug-and-play and power management events occur on operating systems that
support these features.
different major or minor versions) to support different capabilities.
that is, not all DMA Engine capabilities are supported on all ports of the chipset.
on that platform. This includes the ability to detect and use version specific
capabilities and restrictions.
Priority) for exclusive use.
are no longer needed, so other potential clients can claim them.
device (or DMA Engine) to be dynamically removed or (re)inserted and dynamically
powered down and up.
®
5100 MCH Chipset
though
Section 5.17, “DMA Engine Driver”
Intel
®
Section 5.14, “Using DMA
5100 Memory Controller Hub Chipset
describe how the
Datasheet
321