HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 361

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.20.7.1
5.20.7.2
5.20.8
5.20.9
July 2009
Order Number: 318378-005US
A standard PCI Hot Plug* usage model is beneficial to customers who buy systems with
PCI Hot Plug* slots because many customers utilize hardware and software from
different vendors. A standard usage model allows customers to use the PCI Hot Plug*
slots on all of their systems without having to retrain operators.
In order to define a programming model for the Standard PCI Hot Plug* Controller
(SHPC), it is necessary to make some assumptions about the interface between a
human operator and a PCI Hot Plug* slot. The SHPC programming model includes two
indicators, one optional push button, and a sensor on the manually-operated retention
latch for each supported slot.
PCI Hot Plug* Indicators
The Standard Usage Model assumes that the platform provides two indicators per slot
(the Power Indicator and the Attention Indicator). Each indicator is in one of three
states: on, off, or blinking. PCI Hot Plug* system software has exclusive control of the
indicator states by issuing commands to the SHPC.
The SHPC controls blink frequency, duty cycle, and phase. Blinking indicators operate
at a frequency of 1.5 Hz and 50% (+/- 5%) duty cycle. Both indicators are completely
under the control of system software.
Attention Button
An Attention Button is a momentary-contact push-button, located adjacent to each PCI
Hot Plug* slot, that is pressed by the user to initiate a hot-insertion or a hot-removal at
that slot. The Power Indicator provides visual feedback to the human operator (if the
system software accepts the request initiated by the Attention Button) by blinking.
Once the Power Indicator begins blinking, a 5-second abort interval exists during which
a second depression of the Attention Button cancels the operation. Software has the
responsibility to implement this 5-second abort interval.
PCI Hot Plug* Controller
PCI Hot Plug* requires that the Intel
controller for every PCI Hot Plug*-able interface. The PCI Hot Plug* controller is a
capability of the bridge configuration space and the register set is accessible through
the standard PCI capability mechanism defined in the PCI Express* Base Specification,
Rev. 1.0a.
PCI Hot Plug* Usage Model
Not all concepts from the PCI Hot Plug* definition apply directly to PCI Express*
interfaces. The PCI Express* Base Specification, Rev. 1.0a still calls for an identical
software interface in order to facilitate adoption with minimal development overhead on
this aspect of the implementation. The largest variance from the old PCI Hot Plug*
model is in control of the interface itself. PCI required arbitration support for idling
already connected components, and “quick switches” to isolate the bus interface pins of
a PCI Hot Plug* slot. PCI Express* is a point-to-point interface, making PCI Hot Plug* a
degenerate case of the old model that doesn’t require such arbiter support.
Furthermore, the PCI Express* interface is inherently tolerant of hot connect or
disconnect, and does not have explicit clock or reset pins defined as a part of the bus
(although they are standard pieces of some defined PCI Express* connector form
factors). As a result of these differences, some of the inherited PCI Hot Plug* command
and status codes are misleading when applied to PCI Express*.
®
5100 MCH Chipset
®
5100 MCH Chipset implement a PCI Hot Plug*
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
361