HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 70

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.3
3.3.1
3.3.2
Intel
Datasheet
70
®
5100 Memory Controller Hub Chipset
Routing Configuration Accesses
The Intel
mechanisms as defined in the PCI Local Bus Specification, Rev. 2.3. PCI Local Bus
Specification, Rev. 2.3 defines hierarchical PCI busses. Type 0 configuration accesses
are used for registers located within a PCI device that resides on the local PCI bus, i.e.,
the PCI bus on which the transaction is initiated. Type 0 configuration transactions are
not propagated beyond the local PCI bus. Type 0 configuration transactions must be
claimed by a local device or master aborted.
Type 1 configuration accesses are used for devices residing on subordinate PCI buses,
i.e., devices that are connected via PCI-to-PCI bridges. All targets except PCI-to-PCI
bridges ignore Type 1 configuration transactions. PCI-to-PCI bridges decode the bus
number information in Type 1 transactions. If the transaction is targeted to a device
local to the PCI-to-PCI bridge, it is translated into a Type 0 transaction and issued to
the device. If the transaction is targeted to a bus subordinate to (behind) the PCI-to-
PCI bridge, it passed through unchanged. Otherwise the Type 1 transaction is dropped.
Accesses to non-operational or non existent devices are master aborted. This means
that writes are dropped and reads return all 1s.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot-based “configuration space” that supports up to 32 devices.
Each device is allowed to contain up to eight functions with each function containing up
to 256, 8-bit configuration registers. The PCI Local Bus Specification, Rev. 2.3 defines
two bus cycles to access the PCI configuration space: Configuration Read and
Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the
MCH. The PCI Local Bus Specification, Rev. 2.3 defines the configuration mechanism to
access configuration space. The configuration access mechanism makes use of the
CONFIG_ADDRESS Register (at I/O address 0CF8h through 0CFBh) and CONFIG_DATA
Register (at I/O address 0CFCh through 0CFFh). To reference a configuration register a
DWord I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the
PCI bus, the device on that bus, the function within the device, and a specific
configuration register of the device function being accessed. CONFIG_ADDRESS[31]
must be set to 1b to enable a configuration cycle. CONFIG_DATA then becomes a
window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the MCH
translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal MCH configuration
registers.
PCI Bus 0 Configuration Mechanism
The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a device on PCI Bus 0.
The ESI bridge entity within the MCH is hardwired as Device 0 on PCI Bus 0. The ESI
bridge passes PCI south bridge configuration requests to the south bridge. The ICH9R
is the south bridge device for the Intel
®
5100 MCH Chipset supports both PCI Type 0 and Type 1 configuration access
®
5100 MCH Chipset platform.
Intel
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009