HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 372

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 123.
Intel
Datasheet
372
PCI Express* Errors
IO0
IO1
IO2
IO3
IO4
IO5
Notes:
1.
2.
ERR #
MCH
in
®
1
5100 Memory Controller Hub Chipset
IO3 error logging in Intel
ECN (Dec. 2004). However, PEXLNKSTS.TERR provides training indication.
Aliased uncorrectable errors are uncorrectable errors that masquerades as correctable errors to the Memory Controller.
PCI Express* -
Data Link Layer
Protocol Error
PCI Express* -
Received Fatal
Error Message
PCI Express* -
Received
Unsupported
Request
PCI Express* -
Training Error
PCI Express* -
Poisoned TLP
PCI Express* -
Flow Control
Protocol Error
Error Name
Intel
®
5100 Memory Controller Hub Chipset Error List (Sheet 4 of 7)
MCH detects a DL layer
protocol error from the
DLLP.
MCH received a Fatal error
message from the south
bridge.
Received an unsupported
request, similar to master
abort.
PCI Express* link initially
trained successfully, but
failed re-training.
Received a poisoned
transaction layer packet
from the south bridge.
MCH has detected a PCI
Express* Flow Control
Protocol Error
®
5100 MCH Chipset has been defeatured due to PCI Express* Base Specification, Rev. 1.0a
Definition
=UnCorr
=UnCorr
UNCERR
UNCERR
UNCERR
UNCERR
UNCERR
Default
(Check
Default
(Check
Default
(Check
Default
(Check
Default
(Check
=Fatal
=Fatal
=Fatal
Error
Type
SEV)
Fatal
SEV)
SEV)
SEV)
SEV)
and other I/O errors based
respective Error types and
Log PEX_FAT_FERR/NERR
Log the first error pointer
Log UNCERRSTS for their
Log CORERRSTS for their
Log PEXDEVSTS for IO12
or PEX_NF_COR_FERR/
Log RPERRSTS for IO1,
Severity (UNCERRSEV)
respective Error Types.
respective Error Types.
NERR based on their
for UNCERRSTS in
Intel
on UNCERRSEV.
IO11 and IO17.
AERRCAPCTRL.
Log Register
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Log header of packet. The
header log may be not valid
for all cases of unsupported
request.
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Removed by PCI-SIG Errata
to PCI Express* Base
Specification, Rev. 1.0a. No
longer supported.
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Log header of packets with
errors
Check corresponding bit in
UNCERRSEV register for
severity level (Fatal or Non
Fatal)
Cause/Actions
July 2009