HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 3

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
Contents
1.0
2.0
3.0
July 2009
Order Number: 318378-005US
Introduction ............................................................................................................ 22
1.1
1.2
1.3
Signal Description ................................................................................................... 33
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
Register Description ................................................................................................ 65
3.1
3.2
3.3
3.4
3.5
Terminology ..................................................................................................... 22
Related Documents and Materials ........................................................................ 29
Intel
Processor Front Side Bus Signals ......................................................................... 35
2.1.1
2.1.2
DDR2 Memory Channels ..................................................................................... 44
2.2.1
2.2.2
PCI Express* Signal List ..................................................................................... 48
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
SMBus Interfaces .............................................................................................. 52
Extended Debug Port (XDP) Signal List................................................................. 53
JTAG Bus Signal List .......................................................................................... 53
Clocks, Reset and Miscellaneous .......................................................................... 54
Power and Ground Signals .................................................................................. 55
Intel
Reset Requirements........................................................................................... 60
2.10.1 Timing Diagrams .................................................................................... 60
2.10.2 Reset Timing Requirements ..................................................................... 62
2.10.3 Miscellaneous Requirements and Limitations .............................................. 63
Intel
Topology .......................................................................................................... 64
Signals Used as Straps ....................................................................................... 64
2.12.1 Functional Straps ................................................................................... 64
Register Terminology ......................................................................................... 65
Platform Configuration Structure ......................................................................... 66
Routing Configuration Accesses ........................................................................... 70
3.3.1
3.3.2
3.3.3
Device Mapping................................................................................................. 71
3.4.1
I/O Mapped Registers ........................................................................................ 73
3.5.1
3.5.2
®
5100 MCH Chipset
®
®
®
5100 Memory Controller Hub Chipset Overview............................................ 30
5100 Memory Controller Hub Chipset Sequencing Requirements .................... 59
5100 Memory Controller Hub Chipset Customer Reference Platform (CRP) Reset
2.10.1.1 Power-Up................................................................................. 60
2.10.1.2 Power Good ............................................................................. 61
2.10.1.3 Hard Reset............................................................................... 61
2.10.1.4 RESETI# Retriggering Limitations ............................................... 62
Processor Front Side Bus 0 ...................................................................... 35
Processor Front Side Bus 1 ...................................................................... 40
DDR2 Channel 0..................................................................................... 44
DDR2 Channel 1..................................................................................... 46
PCI Express* Common Signals ................................................................. 48
PCI Express* Port 0, Enterprise South Bridge Interface (ESI) ....................... 48
PCI Express* Port 2 ................................................................................ 49
PCI Express* Port 3 ................................................................................ 49
PCI Express* Port 4 ................................................................................ 50
PCI Express* Port 5 ................................................................................ 50
PCI Express* Port 6 ................................................................................ 50
PCI Express* Port 7 ................................................................................ 51
PCI Express* Graphics Port...................................................................... 51
Standard PCI Bus Configuration Mechanism ............................................... 70
PCI Bus 0 Configuration Mechanism .......................................................... 70
Primary PCI and Downstream Configuration Mechanism............................... 71
Special Device and Function Routing ......................................................... 72
CFGADR: Configuration Address Register................................................... 73
CFGDAT: Configuration Data Register ....................................................... 74
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
3