HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 120

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 53.
3.8.8.16
Intel
Datasheet
120
®
5100 Memory Controller Hub Chipset
Intel
Parity Error RAS Handling
1. In general, the DPE field is the superset of the MDPERR from a virtual PCI-to-PCI bridge perspective but there
MBASE[7:2] - Memory Base
The Memory Base and Memory Limit registers define a memory mapped I/O non-
prefetchable address range (32-bit addresses) and the MCH directs accesses in this
range to the PCI Express* port based on the following formula:
The upper 12 bits of both the Memory Base and Memory Limit registers are read/write
and corresponds to the upper 12 address bits, AD[31:20], of 32-bit addresses. For the
purpose of address decoding, the bridge assumes that the lower 20 address bits,
AD[19:0], of the memory base address are zero. Similarly, the bridge assumes that the
lower 20 address bits, AD[19:0], of the memory limit address (not implemented in the
Memory Limit register) are FFFFFh. Thus, the bottom of the defined memory address
range will be aligned to a 1 MB boundary and the top of the defined memory address
range will be one less than a 1 MB boundary. Refer to
Region,” Section 4.4.2, “Address Disposition for Processor,”
Transactions”
Device:
Function:
Offset:
Device:
Function:
Offset:
15:4
4:0
may be cases where a PEXSTS[8].MDPERR may not be logged in the PEXSTS[15].DPE field in the Intel
MCH Chipset on the primary side.
3:0
Bit
Bit
7
6
5
MEMORY_BASE <= A[31:20] <= MEMORY_LIMIT
®
SECSTS[8].SMDPERR
PEXSTS[8].MDPERR
SECSTS[15].SDPE
5100 Memory Controller Hub Chipset PEXSTS and SECSTS Master/Data
PEXSTS[15].DPE
Register Name
Attr
Attr
RW
RO
RO
RO
RV
RV
2-3, 4-7
0
1Eh
2-3, 4-7
0
20h
for further details on address mapping.
Default
Default
0h
0h
0h
0
0
0
1
SFB2BTC: Fast Back-to-Back Transactions Capable
Not applicable to PCI Express*. Hardwired to 0.
Reserved (by PCI-SIG)
S66MHCAP: 66 MHz capability
Not applicable to PCI Express*. Hardwired to 0.
Reserved. (by PCI-SIG)
MBASE: Memory Base Address
Corresponds to A[31:20] of the memory address on the PCI Express* port.
Reserved. (by PCI-SIG)
OB Post
yes
no
no
no
OB Compl
Intel
yes
yes
no
no
®
Description
Description
5100 MCH Chipset—Register Description
Section 4.3.9, “Main Memory
and
IN Post
Section 4.4.3, “Inbound
Order Number: 318378-005US
yes
no
no
no
IB Compl
yes
yes
no
no
July 2009
®
5100