HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 45

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 7.
July 2009
Order Number: 318378-005US
DDR2 Channel 0 Signals (Sheet 2 of 3)
CH0_DQSN[17:0]
CH0_DQSP[17:0]
CH0_DCLKP[2:0]
CH0_DCLKP[3]
CH0_CS[5:4]#
CH0_CS[3:0]#
CH0_DQ[63:0]
CH0_DRVCRES
CH0_ODT[5:4]
CH0_ODT[3:0]
CH0_CRESRET
/CH0_CS[4]#
CH0_CRES1
CH0_CRES2
Name
®
5100 MCH Chipset
Type
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
Memory Channel 0 DDR Clock Negative (Clock 3)/Chip Select (bit 4):
When 48GB_Mode is strapped High, the signal functions as CH0_CS[4]#. This
is to enable chip select signal to the fifth rank on channel 0.
When 48GB_Mode is strapped Low, the signal functions as CH0_DCLKP[3], the
positive polarity of fourth DRAM Clock on channel 0 (Registered DIMMs, no
unbuffered).
Memory Channel 0 DDR Clock Positive (Clocks 2:0):
Positive polarity of DRAM Clock (Registered DIMMs, no unbuffered). The first
three clocks.
Memory Channel 0 DDR2 Resistive Compensation I/Os:
The DDR circuits generate the logic reference used by inbound receivers by
using CH0_CRES1 and CH0_CRES2. The CH0_CRES2 connects to the same
power supply that is used by the DRAM drivers while CH0_CRES1 is connected
to the board ground. By using an internal divider network, various required
reference points can be generated.
Memory Channel 0 Compensation Reference Return VSS:
Internal ground reference for the impedance and slew rate reference resistors.
Memory Channel 0 Chip Select:
When 48GB_Mode is strapped High, these signals in addition to CH0_CS[3:0]#
specify the SDRAM command in combination with CH0_CAS#, CH0_RAS# and
CH0_WE#. CH0_CS[5:0]# select one of six possible ranks, where CH0_CS[0]#
selects the first rank and CH0_CS[5]# selects the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH0_DCLKN[3]
and CH0_DCLKP[15], respectively.
Memory Channel 0 Chip Select:
When 48GB_Mode is strapped High, these signals in addition to CH0_CS[5:4]#
specify the SDRAM command in combination with CH0_CAS#, CH0_RAS# and
CH0_WE#. CH0_CS[5:0]# select one of six possible ranks, where CH0_CS[0]#
selects the first rank and CH0_CS[5]# selects the sixth rank.
When 48GB_Mode is strapped Low, the signals specify the SDRAM command in
combination with CH0_CAS#, CH0_RAS# and CH0_WE#. Selects one of four
possible ranks, where CH0_CS[0]# selects the first rank and CH0_CS[3]#
selects the fourth rank.
Memory Channel 0 Data Bus:
64-bit data bus
Memory Channel 0 Data Strobe Negative:
Negative polarity of Strove. Strobe for correction bits, CH0_CB[7:0], and data
bus, CH0_DQ[63:0]. Each nibble of the 64-bit data bus and 8-bit check bit bus
are associated with a strobe signal for a total of 18 strobe signals.
Memory Channel 0 Data Strobe Positive:
Positive polarity of Strove. Strobe for correction bits, CH0_CB[7:0], and data
bus, CH0_DQ[63:0]. Each nibble of the 64-bit data bus and 8-bit check bit bus
are associated with a strobe signal for a total of 18 strobe signals.
Memory Channel 0 Driver Impedance Compensation Resistor:
Memory Channel 0 On Die Termination (Bits 5:4):
When 48GB_Mode is strapped High, these signals in addition to CH0_ODT[3:0]
operate as the dynamic on die termination enables for each of up to six ranks
on channel 0, where CH0_ODT[0] is for the first rank and CH0_ODT[5] is for
the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH0_CKE[3] and
CH0_A[15], respectively.
Memory Channel 0 On Die Termination (Bits 3:0):
When 48GB_Mode is strapped High, these signals in addition to CH0_ODT[5:4]
operate as the dynamic on die termination enables for each of up to six ranks
on channel 0, where CH0_ODT[0] is for the first rank and CH0_ODT[5] is for
the sixth rank.
When 48GB_Mode is strapped Low, these signals function as CH0_CKE[3] and
CH0_A[15], respectively.
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
45