HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 19

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Revision History—Intel
Revision History
July 2009
Order Number: 318378-005US
June 2009
July 2009
July 2008
Date
Revision Description
005
004
003
®
5100 MCH Chipset
Global Changes:
Register Changes:
Functional Description:
• Change Bit description in
• Changed DQS and DQS Lanes data in
• Removed description from bit 31:0 in
• Clarified that FSB{0/1}RS[2:0]# and FSB{0/1}RSP# signals are outputs only.
•
•
•
•
3”
Data Error Log Register A” on page
Section 3.9.1.4, “MCDEF3: MCDEF Register 3”
Section 3.9.6.12, “REDMEMB[1:0]: Recoverable Memory Data Error Log Register B”
DQS column to
Section 3.12, “PCI Express* Per-Port Registers”
Combining capabilities. Also defeatured PCI Express* Interconnect-Built-In-Self-Test (IBIST)
registers.
Table 117, “PCI Hot Plug* Signals on Virtual Pin Port”
Table 67, “ECC Locator Mapping
Section 3.8.8.33, “PEXCTRL3[7:2,0] - PCI Express* Control Register
206.
Section 3.9.6.11, “REDMEMA[1:0]: Recoverable Memory
Table
67.
corrected offset.
removed all references to PCI Express* Write
Information”.
Intel
added.
®
5100 Memory Controller Hub Chipset
added
Datasheet
19