HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 187

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.9.1.6
July 2009
Order Number: 318378-005US
MTR[1:0][5:0] - Memory Technology Registers
These registers define the organization of the DIMM’s. There is one MTR for each rank.
The parameters for these devices can be obtained by serial presence detect.
MTR[n][5:0] defines ranks [5:0] on channel[n].
This register must not be modified while servicing memory requests.
The following three settings are mutually exclusive:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:11
31:0
• 65,536 rows (NUMROW = “11”)
• 4,096 columns (NUMCOL = “10”)
5:4
3:2
Bit
Bit
10
9
8
7
6
Attr
Attr
RW
RW
RW
RW
RW
RW
RV
RV
RV
®
5100 MCH Chipset
16
1
50h
22, 21
0
1B2h, 1B0h, 15Ah, 158h, 156h, 154h
Default
Default
00h
00
00
0
0
0
0
0
0h
Reserved
PRESENT: Ranks are present
This bit is set if ranks are present and their technologies are compatible.
ETHROTTLE: Technology - Electrical Throttle
Defines the electrical throttling level for these DIMMs:
DRTA.TFAW configuration field.
WIDTH: Technology - Width
Defines the data width of the SDRAMs used on these DIMMs
Reserved
NUMBANK: Technology - Number of Banks
Defines the number of (real, not shadow) banks on these DIMMs
Reserved
NUMROW: Technology - Number of Rows
Defines the number of rows within these DIMMs.
‘0’ = Electrical Throttling is disabled
‘1’ = Electrical Throttling is enabled using the throttling level defined by the
‘0’ = x4 (4 bits wide)
‘1’ = x8 (8 bits wide)
‘0’ = four-banked
‘1’ = eight-banked
“00”
“01”
“10”
“11”
THRESH: Global ERRPER increment threshold
A value of 0 prevents incrementing the error period counter, and therefore the
rank counter, and thus prevents decrementing of CERRCNT. When the value in
this register is reached, the rank counters are incremented by 1.
For example a value of 1G (369AC9FFh) will mean the rank counters increment
one every 16 X 10
= 8,192, 13 rows
= 16,384, 14 rows
= 32,768, 15 rows
= 65,536, 16 rows
9
cycles, where the 16 comes from the initial divide by 16.
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
187