HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 63

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 23.
1. In the Intel
Table 24.
2.10.3
July 2009
Order Number: 318378-005US
Timing
T15
T16
T17
333 MHz, this gives a period of 486 µs for the POC setup time while @266 MHz, the period is 607.5 µs.
Initiation of ESI reset sequence to processor
RESET# signal deassertion
RESETI# re-trigger delay
CPU_RESET_DONE capture timer
®
5100 MCH Chipset, the T11 duration is implemented through a counter with max value of 162,000 core clocks. For
Power Up and Hard Reset Timings (Sheet 2 of 2)
Table 24, “Critical Intel® 5100 Memory Controller Hub Chipset Initialization Timings”
summarizes the Intel
Critical Intel
Miscellaneous Requirements and Limitations
Intel
FSB
Intel
Express* PLL lock
Array initialization
Fuse download
• Power rails and stable BUSCLK, CH{0/1}_DCLK{P/N}, and PECLK master clocks
• Frequencies (for example, 266/333 MHz) described in this section are nominal. The
• Hard Reset can be initiated by code running on a processor, SMBus, or PCI agents.
• Hard Reset is not guaranteed to correct all illegal configurations or malfunctions.
• System activity is initiated by a request from a processor bus. No I/O devices will
• The default values of the Power-On-Configuration (POC) register bits do not require
• Cleanly aborting an in-progress SPD command during a PWRGOOD deassertion is
remain within specifications through all but power-up reset.
Intel
range specified in
Software can configure sticky bits in the Intel
interfaces that will not be accessible after Hard Reset. Signaling errors or protocol
violations prior to reset (from processor bus or PCI Express*) may hang interfaces
that are not cleared by Hard Reset. A PWRGOOD or power-on reset is required to
clear these conditions, if present.
initiate requests until configured by a processor to do so.
any processor request signals to be asserted when PWRGOOD is first asserted.
Software sets these configuration registers to define these values, then initiates a
hard reset that causes them to be driven during processor RESET# signal
assertion.
problematic. No guarantee can be issued as to the final state of the EEPROM in this
situation. The Intel
specification. Since the Intel
up on the platform, a read will not degrade to a write. However, if the PWRGOOD
deassertion occurs after the EEPROM has received the write bit, the data will be
corrupted. The platform pull-up must be strong enough to complete a low-to-high
®
®
5100 MCH Chipset Core,
5100 MCH Chipset PCI
®
Description
®
5100 MCH Chipset
Sequence
5100 MCH Chipset reset sequences must work for the frequency of operation
®
5100 Memory Controller Hub Chipset Initialization Timings
®
Section 5.22, “Clocking.”
®
5100 MCH Chipset Initialization timings.
5100 MCH Chipset cannot meet the SPD data t
Stable power and master clock
Stable power and master clock
Synchronized RESETI#
Deassertion
PWRGOOD Assertion
T5 + T9
2,000
BUSCLK’s
®
5100 MCH Chipset floats the data output into a pull-
Min
Started by
10,000
PECLKs +
T17
Max
®
5100 MCH Chipset to disable
ICH9R specification.
See
See
No Figure reference.
Intel
666,667 333 MHz cycles
200,000 100 MHz cycles
200 cycles
333,333 333 MHz cycles
Figure
Figure
®
Maximum Length
5100 Memory Controller Hub Chipset
5,
8.
Figure 6
Comments
and
SU, STO
Figure
T1
T13
T9
Covered by
parameter
Timing
7.
Datasheet
timing
63