HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 176

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.13.4
3.8.13.5
3.8.13.6
3.8.13.7
Intel
Datasheet
176
®
5100 Memory Controller Hub Chipset
FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register
NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register
This register logs all FSB subsequent errors after the FERR_FAT_FSB has logged the
first fatal error.
NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register
This register logs all FSB subsequent errors after the FERR_NF_FSB has logged the first
fatal error.
NRECFSB[1:0]: Non Recoverable FSB Error Log Register
FSB Log registers for non recoverable errors when a fatal error is logged in its
corresponding FERR_FAT_FSB Register
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
7:3
7:6
2:1
7:3
Bit
Bit
Bit
2
1
0
5
4
3
0
2
1
0
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
RWCST
Attr
Attr
Attr
RV
RV
RV
RV
RV
16
0
481h, 181h
16
0
482h, 182h
16
0
483h, 183h
Default
Default
Default
0h
00
0h
0h
0h
0
0
0
0
0
0
0
0
0
Reserved
F7Err: Detected MCERR from a processor
F8Err: Detected BINIT from a processor
F6Err: Parity Error in Data from FSB Interface
Reserved
F9Err: FSB protocol Error
Reserved
F2Err: Unsupported Processor Bus Transaction
Reserved
F1Err: Request/Address Parity Error
Reserved
F7Err: Detected MCERR from a processor
F8Err: Detected BINIT from a processor
F6Err: Parity Error in Data from FSB Interface
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Description
Order Number: 318378-005US
July 2009