HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 307

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.12.2
5.12.2.1
5.12.2.2
5.12.3
5.12.4
5.12.5
July 2009
Order Number: 318378-005US
Power Management Support
The ICH9R provides a rich set of power management capabilities for the operating
system. The MCH receives PM_PME messages on its standard PCI Express* port and
propagates it to the ICH9R over the ESI as an Assert_PMEGPE message. When
software clears the PEXRTSTS.PME Status register bit, in the PEXRSTSTS[7:2,0] PCI
Express* Root Status Register, after it has completed the PME protocol, the MCH will
generate a Deassert_PMEGPE message to the ICH9R. The MCH must also be able to
generate the Assert_PMEGPE message when exiting S3 (after the reset). The PMGPE
messages are also sent using a wired-OR approach.
Rst_Warn and Rst_Warn_Ack
The Rst_Warn message is generated by the ICH9R as a warning to the MCH that it
wants to assert PLTRST# before sending the reset. In the past, problems have been
encountered due to the effects of an asynchronous reset on the system memory states.
Since memory has no reset mechanism itself other than cycling the power, it can cause
problems with the memory’s internal states when clocks and control signals are
asynchronously tristated or toggled, if operations resume following this reset without
power cycling. To protect against this, the ICH9R will send a reset warning to the MCH.
The Intel
Intel
asserted.
The MCH completes the handshake by generating the Rst_Warn_Ack message to the
ICH9R at the earliest.
STPCLK Propagation
The ICH9R has a sideband signal called STPCLK. This signal is used to place IA-32 CPUs
into a low power mode. Traditionally, this signal has been routed directly from the I/O
controller hub to the CPUs.
Special Interrupt Support
The ICH9R integrates an I/O APIC controller. This controller is capable of sending
interrupts to the processors with an inbound write to a specific address range that the
processors recognize as an interrupt. In general, the compatibility interface cluster
treats these no differently from inbound writes to DRAM. However, there are a few
notable differences listed below.
Inbound Interrupts
To the MCH, interrupts from the ICH9R are simply inbound non-coherent write
commands routed to the processor buses. The MCH does not support the serial APIC
bus.
Legacy Interrupt Messages
The ESI and PCI Express* interfaces support two methods for handling interrupts: MSI
and legacy interrupt messages. The interrupt messages are a mechanism for taking
traditionally out-of -band interrupt signals and using in-band messages to
communicate. Each PCI Express* interface accepts up to four interrupts (A through D)
and each interrupt has an assert/deassert message to emulate level-triggered
behavior. The MCH effectively wire-ORs all the INTA messages together (INTBs are
wire-ORed together, etc.).
®
5100 MCH Chipset does not put the DIMMs in self-refresh when PLTRST# is
®
®
5100 MCH Chipset is NOT required to quiesce the DRAM’s prior to reset. The
5100 MCH Chipset
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
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