HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 115

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
10:9
Bit
15
14
13
12
11
8
7
6
5
4
3
®
RWC
RWC
RWC
RWC
RWC
Attr
RO
RO
RO
RO
RO
RO
RV
5100 MCH Chipset
7-2, 0
0
06h
Default
0h
0
0
0
0
0
0
0
0
0
1
0
DPE: Detected Parity Error
This bit is set when the PCI Express* port receives an uncorrectable data error
or Address/Control parity errors regardless of the Parity Error Response
Enable bit (PERRE). This applies only to parity errors that target the PCI
Express* port interface (inbound/outbound direction). The detected parity
error maps to B1, F6, M2 and M4 (uncorrectable data error from FSB, Memory
or internal sources) of the Intel
SSE: Signaled System Error
1: The PCI Express* port generated internal FATAL/NON FATAL errors (IO0-
IO17) through the ERR[2:0] pins with SERRE bit enabled. Software clears this
bit by writing a ‘1’ to it.
0: No internal PCI Express* port errors are signaled.
RMA: Received Master Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Unsupported Request
Completion Status.
1: Assert this RMA bit when the primary side performs operations for an
unsupported transaction. These apply to inbound configs, I/O accesses, locks,
bogus memory reads and any other request that is master aborted internally.
These are terminated on the PCI Express* link with a UR completion status,
but only if a completion is required. Software clears this bit by writing a 1 to it.
PEXDEVSTS.URD is set and UNCERRSTS[20].IO2Err is set in addition.
0: No Master Abort is generated
RTA: Received Target Abort
This bit is set when a requestor (primary side for Type 1 header configuration
space header device) receives a completion with Completer Abort Completion
Status, e.g., for supported requests that cannot be completed because of
address decoding problems or other errors. These are terminated on the PCI
Express* link with a CA completion status, but only if a completion is required.
Software clears this bit by writing a 1 to it.
STA: Signaled Target Abort
Target Abort does not exist on the primary side of the PCI Express* port.
Hardwired to 0.
DEVSELT: DEVSEL# Timing
Not applicable to PCI Express*. Hardwired to 0.
MDPERR: Master Data Parity Error
This bit is set by the PCI Express* port if the Parity Error Response Enable bit
(PERRE) is set and it receives error B1, F2, F6, M2 and M4 (uncorrectable data
error or Address/Control parity errors or an internal failure). If the Parity Error
Enable bit (PERRE) is cleared, this bit is never set.
FB2B: Fast Back-to-Back
Not applicable to PCI Express*. Hardwired to 0.
Reserved. (by PCI-SIG)
66MHZCAP: 66 MHz capable.
Not applicable to PCI Express*. Hardwired to 0.
CAPL: Capabilities List
This bit indicates the presence of PCI Express* capabilities list structure in the
PCI Express* port. Hardwired to 1. (Mandatory)
INTxSTAT: INTx Status
Indicates that an INTx interrupt message is pending internally in the PCI
Express* port.
The INTx status bit should be rescinded when all the relevant events via RAS
errors/HP/PM internal to the port that requires legacy interrupts are cleared by
software.
®
Description
5100 MCH Chipset.
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
115