HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 184

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Intel
Datasheet
184
®
5100 Memory Controller Hub Chipset
Device:
Function:
Offset:
28:25
24:22
19:18
17:14
11:9
Bit
30
29
21
20
13
12
8
Attr
RW
RW
RW
RW
RW
RW
RW
RV
RV
RV
RV
RV
16
1
40h
Default
0h
0h
00
0h
0h
0
0
0
0
0
0
0
RETRY: Retry Enable:
Retry uncorrectable ECC error (more than single bit error)
‘1’ = enables retry.
‘0’ = disables retry.
Reserved
BADRAMTH: BADRAM Threshold
Number of consecutive instances of adjacent symbol errors required to mark a bad
device in a rank. Number of patrol scrub cycles required to decrement a non-
saturated BADCNT.
If Software desires to enable the “enhanced mode” and use the BADRAMTH, it
needs to set a non-zero value to this register field prior. Otherwise, a value of 0 is
considered illegal and memory RAS operations may lead to indeterministic
behavior.
Reserved
INITDONE: Initialization Complete. This scratch bit communicates software
state from the Intel
initialization of the DRAM memory array is complete. This bit has no effect on the
Intel
Reserved
PHT: Page Hit Threshold
Determines max allowable page hits before a page will be precharged. A page hit is
a consecutive CAS access the same page (which has been left open). If there is no
available page hit, then autoprecharge will occur.
00: 0 (no hit allowed, all accesses are with autoprecharge)
01: 1
10: 3
11: 7 (Up to 7 hits allowed => max 8 accesses to a page before it is closed)
Note: This field alters the address interleaving scheme depending on whether it is
00 or not. Modifying this field will therefore invalidate the DRAM contents.
Reserved
FSMEN1: Channel 1 Enable.
‘1’ = Enables operation of DDR protocol. This can be used as a synchronous
reset to the FSM. (normal)
‘0’ = Inhibits processing of enqueued transactions. Disables all DRAM
accesses :
a) memory reads
b) memory writes
c) refreshes
Not preserved by SAVCFG
FSMEN0: Channel 0 Enable.
‘1’ = Enables operation of DDR protocol. This can be used as a synchronous
reset to the FSM. (normal)
‘0’ = Inhibits processing of enqueued transactions. Disables all DRAM
accesses :
a) memory reads
b) memory writes
c) refreshes
Not preserved by SAVCFG
Reserved
SCRBALGO: Enhanced Mode Algorithm for x8 uncorrectable error detection
0: Normal mode where BADRAM is not used to flag bad devices.
1: Enhanced mode where BADRAM is used to flag bad devices.
®
5100 MCH Chipset operation.
®
5100 MCH Chipset to BIOS. BIOS sets this bit to 1 after
Intel
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
July 2009