HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 9

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Contents—Intel
4.0
July 2009
Order Number: 318378-005US
System Address Map ............................................................................................. 258
4.1
4.2
4.3
4.4
4.5
System Memory Address Ranges ....................................................................... 258
4.1.1
Compatibility Area ........................................................................................... 261
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
System Memory Area....................................................................................... 264
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
Memory Address Disposition ............................................................................. 269
4.4.1
4.4.2
4.4.3
I/O Address Map ............................................................................................. 275
4.5.1
®
5100 MCH Chipset
3.12.0.3 PPRSETLEN[3:2] - Per-Port Register Set Length Register .............. 252
3.12.0.4 STRMPRI[3:2]: Stream Priority Register..................................... 252
3.12.0.5 REQID[3:2] - Requestor ID Register .......................................... 252
3.12.0.6 STRMCAP[3:2] - Stream Capacity Register ................................. 252
3.12.0.7 STRMIDFMT[3:2] - Stream ID Format Register ........................... 253
3.12.0.8 BRIDGE_ID2 - Bridge ID Register.............................................. 254
3.12.0.9 BRIDGE_ID3 - Bridge ID Register.............................................. 254
3.12.0.10STRMMAP_OFFSET2: Stream Priority Mapping Offset Register ....... 254
3.12.0.11STRMMAP_OFFSET3: Stream Priority Mapping Offset Register ....... 255
3.12.0.12PORTPRI2: Port Priority Register ............................................... 255
3.12.0.13PORTPRI3: Port Priority Register ............................................... 255
3.12.0.14STRM_COMP[3:2] - Stream Priority Compatibility Register ........... 255
3.12.0.15BR_MEM_BASE[3:2] - Bridge Memory Base Register.................... 256
3.12.0.16BR_MEM_LIMIT[3:2] - Bridge Memory Limit Register ................... 256
3.12.0.17BR_PMEM_BASE[3:2] - Bridge Prefetchable Memory Base Register 256
3.12.0.18BR_PMEM_LIMIT[3:2] - Bridge Prefetchable Memory Limit Register 257
3.12.0.19BR_PBASE_UPPER32_P[3:2] - Bridge Prefetchable Base Upper 32
3.12.0.20BR_PLIMIT_UPPER32_P[3:2] - Bridge Prefetchable Limit Upper 32
4.3.7.1
4.3.7.2
4.3.7.3
4.3.7.4
4.3.7.5
4.3.8.1
4.3.8.2
4.3.8.3
4.3.8.4
4.3.9.1
4.3.9.2
4.4.2.1
32/64-bit Addressing ............................................................................ 259
MS-DOS Area (0 0000h–9 FFFFh) ........................................................... 261
Legacy VGA Ranges (A 0000h–B FFFFh) .................................................. 262
Expansion Card BIOS Area (C 0000h–D FFFFh)......................................... 262
Lower System BIOS Area (E 0000h–E FFFFh) ........................................... 263
Upper System BIOS Area (F 0000h–F FFFFh) ........................................... 263
System Memory ................................................................................... 264
15 MB - 16 MB Window (ISA Hole).......................................................... 264
Extended SMRAM Space (TSEG) ............................................................. 264
Memory Mapped Configuration (MMCFG) Region ....................................... 265
Low Memory Mapped I/O (MMIO) ........................................................... 265
Chipset Specific Range .......................................................................... 266
Interrupt/SMM Region........................................................................... 267
High Extended Memory ......................................................................... 268
Main Memory Region ............................................................................ 269
Registers Used for Address Routing......................................................... 270
Address Disposition for Processor ........................................................... 270
Inbound Transactions ........................................................................... 274
Special I/O Addresses ........................................................................... 276
Register................................................................................. 257
Register................................................................................. 257
I/O APIC Controller Range........................................................ 267
High SMM Range..................................................................... 268
Interrupt Range ...................................................................... 268
Reserved Ranges .................................................................... 268
Firmware Range ..................................................................... 268
System Memory ..................................................................... 268
High MMIO............................................................................. 269
CB_BAR MMIO ........................................................................ 269
Extended Memory ................................................................... 269
Application of Coherency Protocol.............................................. 269
Routing Memory Requests........................................................ 269
Access to SMM Space (Processor Only) ...................................... 272
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
9