HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 129

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
25:24
Bit
23
22
®
5100 MCH Chipset
Attr
RW
RW
RW
7-2,0
0
48h
Default
00
0
0
COALESCE_MODE: Used to increase the amount of combining for
completions.
00: No restriction on coalescing_hint. The IOU will try to maximize
completion combining. Since the Intel
requests in order, it does not make sense to restrict the coalesce hint
because there are few
resources available at the time of fetch. By the time the hint is used,
resources could be freed up and reused for the following requests
Note:
01: #CPL_ENTRIES_FREE will restrict coalesce_hint
10: if set then #PF_PEND will restrict coalesce hint
11: Minimum of coalesce_hint obtained from settings “01” and “10”
TIMEOUT_ENABLE_CFG: Timeout enable for configuration
transactions
1: Config transactions can time out.
0: Config transactions cannot time out.
Suggested value: 0
Note:
Note:
Note:
TIMEOUT_ENABLE: Timeout enable for non-configuration
transactions
1: Non config transactions can time out.
0: Non config transactions cannot time out.
Suggested value: 1
Note:
Note:
This mode of “00” is the preferred setting for the Intel
MCH Chipset if COALESCE_EN=1 for software/BIOS
In general, configuration timeouts on the PCI Express* port
should not be enabled. This is necessary to permit slow devices
nested deep in the PCI hierarchy that may take longer to
complete requests than the maximum timeout specified in the
Intel
based on the context and usage/platform configuration. For
example, compliance testing with a known broken card should
have this field set.
For the configuration timeout to take effect, the
PEXCTRL.TIMEOUT_ENABLE (bit 22) has to be set.
In the MCH, the IOU will log a completion timeout error (IO6) for
any outstanding configuration transaction that crosses the
counter limit even if this register field is cleared or bit 22 of this
register is cleared (i.e., either timeout is disabled). However, it
does not affect the functionality and the config transaction will
be outstanding indefinitely till a completion is returned except
for the unnecessary error log. Software should be aware of this
limitation when the field is cleared.
When both TIMEOUT_ENABLE_CFG and TIMEOUT_ENABLE fields
are set to 0, the Intel
completion time for the respective transactions. Hence the
system is dependent on the end device returning the completion
response at some point in time, else it will result in a hang.
In the MCH, the IOU will log a completion timeout error (IO6) for
any outstanding non-configuration transaction that crosses the
counter limit even if this register field is cleared (i.e., timeout is
disabled). However, it does not affect the functionality and the
non config-transaction will be outstanding indefinitely till a
completion is returned except for the unnecessary error log.
Software should be aware of this limitation when the field is
cleared.
®
5100 MCH Chipset. Software/BIOS should set this field
®
Description
Intel
5100 MCH Chipset will assume an infinite
®
®
5100 Memory Controller Hub Chipset
5100 MCH Chipset issues
®
Datasheet
5100
129