HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 229

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Figure 14.
3.11.13
July 2009
Order Number: 318378-005US
Intel
Interrupt Handling Flow
MSIAR: Message Signaled Interrupt Address Register
Device:
Function:
Offset:
31:20
19:12
11:4
Bit
3
®
5100 Memory Controller Hub Chipset DMA Error/Channel Completion
MSIEN
®
Attr
RW
RW
RW
RO
1
1
0
0
5100 MCH Chipset
8
0
5Ch
Default
FEEh
0h
0h
0
MSICBEN
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
AEXDSTID: Address Extended Destination ID
This field is not used by IA-32 processor.
ARDHINT: Address Redirection Hint
0: directed
1: redirectable
DMA errors/completion
1
0
x
x
(MSICTRL.MSIEN
(PEXCMD.INTx
Disable == 1)?
interrupts
== 1)?
Y
N
INTx Disable
0
1
N
x
x
Y
Sends Dssert_INTx
Sends Deassert_INTx
INTRCTRL.intp is
message via ESI
reset (wired-OR)
per INTP when
message via ESI
Description
(DMACTRL.MSICBEN
The MCH
Intel
per INTP
MCH
Assert_INTx
®
== 1)?
5100 Memory Controller Hub Chipset
Output
N
MSI
--
--
Channel completions
Y
MSI For both DMA
MCH sends only 1
interrupts and
per MSIAR an d
MCH sends MSI
0128081131
MSIDR
Datasheet
229