HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 107
HH80556KH0364M S LAGD
Manufacturer Part Number
HH80556KH0364M S LAGD
Description
Manufacturer
Intel
Datasheet
1.HH80556KH0364M_S_LAGD.pdf
(434 pages)
Specifications of HH80556KH0364M S LAGD
Rad Hardened
No
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Register Description—Intel
3.8.5.3
July 2009
Order Number: 318378-005US
POC - Power-On Configuration Register
Contrary to its name, this register defines configuration values driven at reset. At
power-on, no bits in this register are active as PWRGOOD clears them all. This register
only activates configuration on subsequent resets.
The MCH drives the contents of this register on A[35:4]# whenever it asserts processor
RESET#. These values are driven during processor RESET# assertion, and for two host
clocks past the trailing edge of processor RESET#.
This register is sticky through reset; that is, the contents of the register remain
unchanged during and following a Hard Reset. This allows system configuration
software to modify the default values and reset the system to pass those values to all
host bus devices.
The POC bits do not affect MCH operation except for driving A[35:4]#.
Read after write to POC register will read updated value but the architectural behavior
will not be affected until hard reset deassertion. A warm reset (CPU reset) will not
cause the contents of the POC register to be altered.
There are other power-on configuration bits in the SYRE register.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:28
26:12
10:0
Bit
27
11
11:0
Bit
RWST
RWST
Attr
RV
RV
RV
RWST
®
Attr
5100 MCH Chipset
16
0
42h
16
0
44h
Default
Default
7FFh
0h
0h
0h
0
1
DCRT: ESI CPU Reset Done Ack Determinism Timer
This field provides the determinism timer threshold for the Intel
Chipset for handling the CPU_RESET_DONE/CPU_RESET_DONE_ACK
message before deasserting the CPU_RESET#. It uses this 12-bit counter to
schedule the CPU_RESET_DONE message on the ESI and then waits for the
CPU_RESET_DONE_ACK message to come back and waits for the timer
expiry before deasserting CPU_RESET#.
Cap_latency = Max(CPU_RST_DONE_ACK_round trip_latency, DCRT).
It is expected that the DCRT field is set larger than the expected round trip
latency. This provides the necessary leeway for absorbing clock
synchronization, jitter, deskew and other variations that will affect the
determinism on the ESI port. Hence the data is always sent back only after
the expiry of the DCRT field at the heartbeat boundary.
It is sticky through reset to permit to allow different types of BIOS flows that
may require a hard reset of the Intel
Maximum value is 4095 core clocks
A default of 2047 clocks (7FFh) is used.
Reserved
MTDIS: Disable Multi-Threading
If set, A[31]# is asserted, and the processor will disable Multi-threading.
Reserved
BUSPARK: Request Bus Parking Disable
If set, A[15]# is asserted and the processor may not park on the system
bus. Default is to disable busparking
Reserved
Description
Description
Intel
®
®
5100 MCH Chipset.
5100 Memory Controller Hub Chipset
®
5100 MCH
Datasheet
107
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