HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 155

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.11.13
July 2009
Order Number: 318378-005US
PEXRTSTS[7:2,0] - PCI Express* Root Status Register
The PCI Express* Root Status register specifies parameters specific to the root complex
port.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:18
Bit
Bit
17
3
2
1
0
®
Attr
Attr
RW
RW
RW
RW
RO
RV
5100 MCH Chipset
7-2, 0
0
88h
7-2, 0
0
8Ch
Default
Default
0h
0
0
0
0
0
PMEINTEN: PME Interrupt Enable
This field controls the generation of interrupts for PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit defined in the PEXRTSTS register. A PME interrupt is
generated if the PMESTATUS register bit defined in
“PEXRTSTS[7:2,0] - PCI Express* Root Status Register,”
set from a cleared state.
0: Disables interrupt generation for PME messages.
SEFEEN: System Error on Fatal Error Enable
This field controls generation of system errors in the PCI Express* port
hierarchy for fatal errors.
1: Indicates that a System Error should be generated if a fatal error
(ERR_FATAL) is reported by any of the devices in the hierarchy associated with
and including this PCI Express* port.
0: No System Error should be generated on a fatal error (ERR_FATAL) reported
by any of the devices in the hierarchy.
SENFEEN: System Error on Non-Fatal Error Enable
This field controls generation of system errors in the PCI Express* port
hierarchy for non-fatal errors.
1: Indicates that a System Error should be generated if a non-fatal error
(ERR_NONFATAL) is reported by any of the devices in the hierarchy associated
with and including this PCI Express* port.
0: No System Error should be generated on a non-fatal error (ERR_NONFATAL)
reported by any of the devices in the hierarchy.
SECEEN: System Error on Correctable Error Enable
This field controls generation of system errors in the PCI Express* port
hierarchy for correctable errors.
1: Indicates that a System Error should be generated if a correctable error
(ERR_COR) is reported by any of the devices in the hierarchy associated with
and including this PCI Express* port
0: No System Error should be generated on a correctable error (ERR_COR)
reported by any of the devices in the hierarchy associated with and including
this PCI Express* port.
Reserved.
PMEPEND: PME Pending
This field indicates that another PME is pending when the PME Status bit is set.
When the PME Status bit is cleared by software; the pending PME is delivered
by hardware by setting the PME Status bit again and updating the Requestor
ID appropriately. The PME pending bit is cleared by hardware if no more PMEs
are pending.
Note:
The Intel
messages in its internal queues of the Power Management controller
per port. If the downstream device issues more than 2 PM_PME
messages successively, it will be dropped.
®
5100 MCH Chipset can handle two outstanding PM_PME
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Section 3.8.11.13,
is set when this bit is
Datasheet
155