HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 116

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.8.3
3.8.8.4
3.8.8.5
3.8.8.6
3.8.8.7
Intel
Datasheet
116
®
5100 Memory Controller Hub Chipset
CLS[7:2,0] - Cache Line Size
This register contains the Cache Line Size and is set by BIOS/Operating system. It does
not affect the PCI Express* port functionality in the MCH.
PRI_LT[7:2,0] - Primary Latency Timer
This register denotes the maximum time slice for a burst transaction in legacy PCI 2.3
on the primary interface. It does not affect/influence PCI Express* functionality.
BIST[7:2,0] - Built-In Self-test
This register is used for reporting control and status information of BIST checks within
a PCI Express* port. It is not supported in the Intel
BAR0[7:2,0] - Base Address Register 0
Base address registers are used for mapping internal registers to an MMIO or I/O
space. It does not affect the MCH. The base address register 0 is not supported/defined
in the PCI Express* port of the MCH.
BAR1[7:2,0] - Base Address Register 1
The base address register 1 is not supported/defined in the MCH.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
2:0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Attr
Attr
Attr
Attr
RW
RO
RO
RV
7-2, 0
0
06h
7-2, 0
0
0Ch
7-2, 0
0
0Dh
7-2, 0
0
0Fh
Default
Default
Default
Default
00h
00h
00h
0h
Reserved. (by PCI-SIG)
CLS: Cache Line Size
This is an 8-bit value that indicates the size of the cache line and is specified in
DWORDs. It does not affect the MCH.
Prim_Lat_timer: Primary Latency Timer
Not applicable to PCI Express*. Hardwired to 00h.
BIST_TST: BIST Tests
Not supported. Hardwired to 00h
Intel
®
Description
Description
Description
Description
®
5100 MCH Chipset—Register Description
5100 MCH Chipset.
Order Number: 318378-005US
July 2009